[Linaro-uefi,08/11] Hisilicon: Update some headers file to support Hi1616

Message ID 1476324020-57155-8-git-send-email-heyi.guo@linaro.org
State New
Headers show

Commit Message

gary guo Oct. 13, 2016, 2 a.m.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
 Chips/Hisilicon/Include/Library/HwMemInitLib.h     | 60 +++++++++++++++++++---
 .../Hisilicon/Include/Library/PlatformSysCtrlLib.h |  6 +++
 Chips/Hisilicon/Include/PlatformArch.h             |  2 +
 3 files changed, 60 insertions(+), 8 deletions(-)

Comments

Leif Lindholm Oct. 13, 2016, 2:13 p.m. | #1
Needs a message body explaining the types of modifications made.

On Thu, Oct 13, 2016 at 10:00:17AM +0800, Heyi Guo wrote:
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
> ---
>  Chips/Hisilicon/Include/Library/HwMemInitLib.h     | 60 +++++++++++++++++++---
>  .../Hisilicon/Include/Library/PlatformSysCtrlLib.h |  6 +++
>  Chips/Hisilicon/Include/PlatformArch.h             |  2 +
>  3 files changed, 60 insertions(+), 8 deletions(-)
> 
> diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h
> index f424ae9..09aef56 100644
> --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h
> +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h
> @@ -123,8 +123,8 @@ typedef struct _DDR_DIMM{
>      UINT8       MtbDividend;
>      UINT8       MtbDivsor;
>      UINT8       nCL;
> -    UINT8       nRCD;
> -    UINT8       nRP;
> +    UINT32      nRCD;
> +    UINT32      nRP;
>      UINT8       SPDftb;
>      UINT8       SpdMinTCK;
>      UINT8       SpdMinTCKFtb;
> @@ -173,8 +173,14 @@ typedef struct {
>      UINT32      ddrcTiming5;
>      UINT32      ddrcTiming6;
>      UINT32      ddrcTiming7;
> +    UINT32      ddrcTiming8;
>  }DDRC_TIMING;
>  
> +typedef struct _MARGIN_RESULT{
> +    UINT32 OptimalDramVref[12];
> +    UINT32 optimalPhyVref[18];
> +}MARGIN_RESULT;
> +
>  typedef struct _DDR_Channel{
>      BOOLEAN     Status;
>      UINT8       CurrentDimmNum;
> @@ -184,22 +190,42 @@ typedef struct _DDR_Channel{
>      UINT8       DramWidth;
>      UINT8       ModuleType;
>      UINT32      MemSize;
> +    UINT32      tck;
> +    UINT32      ratio;
>      UINT32      CLSupport;
>      UINT32      minTck;
> +    UINT32      taref;
> +    UINT32      nAA;
> +    UINT32      nAOND;
> +    UINT32      nCKE;
>      UINT32      nCL;
> -    UINT32      nWR;

This field has just moved.

> +    UINT32      nCCDL;
> +    UINT32      nCKSRX;
> +    UINT32      nCKSRE;
> +    UINT32      nCCDNSW;
> +    UINT32      nCCDNSR;
> +    UINT32      nFAW;
> +    UINT32      nMRD;
> +    UINT32      nMOD;
>      UINT32      nRCD;
>      UINT32      nRRD;
>      UINT32      nRRDL;
>      UINT32      nRAS;
>      UINT32      nRC;
>      UINT32      nRFC;
> -    UINT32      nWTR;

This field has just moved.

> +    UINT32      nRFCAB;
>      UINT32      nRTP;
> -    UINT32      nAA;
> -    UINT32      nFAW;

These fields have just moved.

> +    UINT32      nRTW;
>      UINT32      nRP;
> -    UINT32      nCCDL;

These fields have just moved.

> +    UINT32      nSRE;
> +    UINT32      nWL;
> +    UINT32      nWR;
> +    UINT32      nWTR;
> +    UINT32      nWTRL;
> +    UINT32      nXARD;
> +    UINT32      nZQPRD;
> +    UINT32      nZQINIT;
> +    UINT32      nZQCS;
>      UINT8       cwl;  //tWL?
>      UINT8       pl;     //parity latency
>      UINT8       wr_pre_2t_en;
> @@ -228,15 +254,23 @@ typedef struct _DDR_Channel{
>      UINT8       per_cs_training_en;
>      UINT32      phyRdDataEnIeDly;
>      UINT32      phyPadCalConfig;
> -    UINT32      phyDqsFailRiseDelay;
> +    UINT32      phyDqsFallRiseDelay;

And this appears a typo fix.

Please separate the changes unrelated to the new platform support out
into a separate patch.

/
    Leif

>      UINT32      ddrcCfgDfiLat0;
>      UINT32      ddrcCfgDfiLat1;
>      UINT32      parityLatency;
> +    UINT32      dimm_parity_en;
>      DDRC_TIMING ddrcTiming;
>      DDR_DIMM    Dimm[MAX_DIMM];
> +    MARGIN_RESULT sMargin;
>  }DDR_CHANNEL;
>  
>  typedef struct _NVRAM_RANK{
> +    UINT16      MR0;
> +    UINT16      MR1;
> +    UINT16      MR2;
> +    UINT16      MR3;
> +    UINT16      MR4;
> +    UINT16      MR5;
>      UINT16      MR6[9];
>  }NVRAM_RANK;
>  
> @@ -306,6 +340,14 @@ typedef struct _MEMORY{
>      UINT32          Config2;
>  }MEMORY;
>  
> +typedef struct _NUMAINFO{
> +    UINT8           NodeId;
> +    UINT64          Base;
> +    UINT64          Length;
> +    UINT32          DieInterleaveEn;
> +}NUMAINFO;
> +
> +
>  typedef struct _GBL_DATA
>  {
>      DDR_CHANNEL Channel[MAX_SOCKET][MAX_CHANNEL];
> @@ -319,6 +361,7 @@ typedef struct _GBL_DATA
>      UINT32      SpdTck;
>      UINT32      Tck;
>      UINT32      DdrFreqIdx;
> +    UINT32      DevParaFreqIdx;
>      UINT32      MemSize;
>      UINT32      EccEn;
>  
> @@ -365,6 +408,7 @@ typedef struct _GBL_DATA
>      BOOLEAN     chipIsEc;
>      NVRAM       nvram;
>      MEMORY      mem;
> +    NUMAINFO    NumaInfo[MAX_NODE_TYPE][MAX_NUM_PER_TYPE];
>  
>  }GBL_DATA, *pGBL_DATA;
>  
> diff --git a/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h b/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h
> index f374112..23e1393 100644
> --- a/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h
> +++ b/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h
> @@ -90,8 +90,14 @@ VOID DResetUsb ();
>  UINT32 PlatformGetEhciBase ();
>  UINT32 PlatformGetOhciBase ();
>  VOID PlatformPllInit();
> +VOID SiclPllInit(UINT32 SclId);
>  VOID PlatformDeviceDReset();
>  VOID PlatformGicdInit();
>  VOID PlatformLpcInit();
> +VOID PlatformArchTimerSynchronize();
> +VOID PlatformEventBroadcastConfig();
> +UINTN GetDjtagRegBase(UINT32 NodeId);
> +VOID LlcCleanInvalidateAsm();
> +VOID PlatformMdioInit();
>  
>  #endif
> diff --git a/Chips/Hisilicon/Include/PlatformArch.h b/Chips/Hisilicon/Include/PlatformArch.h
> index f1ccbb6..b34f62f 100644
> --- a/Chips/Hisilicon/Include/PlatformArch.h
> +++ b/Chips/Hisilicon/Include/PlatformArch.h
> @@ -26,6 +26,8 @@
>  #define MAX_DIMM        3
>  #define MAX_RANK_CH     12
>  #define MAX_RANK_DIMM   4
> +#define MAX_NODE_TYPE   4
> +#define MAX_NUM_PER_TYPE 8
>  
>  #define S1_BASE               0x40000000000
>  
> -- 
> 1.9.1
>

Patch

diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h
index f424ae9..09aef56 100644
--- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h
+++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h
@@ -123,8 +123,8 @@  typedef struct _DDR_DIMM{
     UINT8       MtbDividend;
     UINT8       MtbDivsor;
     UINT8       nCL;
-    UINT8       nRCD;
-    UINT8       nRP;
+    UINT32      nRCD;
+    UINT32      nRP;
     UINT8       SPDftb;
     UINT8       SpdMinTCK;
     UINT8       SpdMinTCKFtb;
@@ -173,8 +173,14 @@  typedef struct {
     UINT32      ddrcTiming5;
     UINT32      ddrcTiming6;
     UINT32      ddrcTiming7;
+    UINT32      ddrcTiming8;
 }DDRC_TIMING;
 
+typedef struct _MARGIN_RESULT{
+    UINT32 OptimalDramVref[12];
+    UINT32 optimalPhyVref[18];
+}MARGIN_RESULT;
+
 typedef struct _DDR_Channel{
     BOOLEAN     Status;
     UINT8       CurrentDimmNum;
@@ -184,22 +190,42 @@  typedef struct _DDR_Channel{
     UINT8       DramWidth;
     UINT8       ModuleType;
     UINT32      MemSize;
+    UINT32      tck;
+    UINT32      ratio;
     UINT32      CLSupport;
     UINT32      minTck;
+    UINT32      taref;
+    UINT32      nAA;
+    UINT32      nAOND;
+    UINT32      nCKE;
     UINT32      nCL;
-    UINT32      nWR;
+    UINT32      nCCDL;
+    UINT32      nCKSRX;
+    UINT32      nCKSRE;
+    UINT32      nCCDNSW;
+    UINT32      nCCDNSR;
+    UINT32      nFAW;
+    UINT32      nMRD;
+    UINT32      nMOD;
     UINT32      nRCD;
     UINT32      nRRD;
     UINT32      nRRDL;
     UINT32      nRAS;
     UINT32      nRC;
     UINT32      nRFC;
-    UINT32      nWTR;
+    UINT32      nRFCAB;
     UINT32      nRTP;
-    UINT32      nAA;
-    UINT32      nFAW;
+    UINT32      nRTW;
     UINT32      nRP;
-    UINT32      nCCDL;
+    UINT32      nSRE;
+    UINT32      nWL;
+    UINT32      nWR;
+    UINT32      nWTR;
+    UINT32      nWTRL;
+    UINT32      nXARD;
+    UINT32      nZQPRD;
+    UINT32      nZQINIT;
+    UINT32      nZQCS;
     UINT8       cwl;  //tWL?
     UINT8       pl;     //parity latency
     UINT8       wr_pre_2t_en;
@@ -228,15 +254,23 @@  typedef struct _DDR_Channel{
     UINT8       per_cs_training_en;
     UINT32      phyRdDataEnIeDly;
     UINT32      phyPadCalConfig;
-    UINT32      phyDqsFailRiseDelay;
+    UINT32      phyDqsFallRiseDelay;
     UINT32      ddrcCfgDfiLat0;
     UINT32      ddrcCfgDfiLat1;
     UINT32      parityLatency;
+    UINT32      dimm_parity_en;
     DDRC_TIMING ddrcTiming;
     DDR_DIMM    Dimm[MAX_DIMM];
+    MARGIN_RESULT sMargin;
 }DDR_CHANNEL;
 
 typedef struct _NVRAM_RANK{
+    UINT16      MR0;
+    UINT16      MR1;
+    UINT16      MR2;
+    UINT16      MR3;
+    UINT16      MR4;
+    UINT16      MR5;
     UINT16      MR6[9];
 }NVRAM_RANK;
 
@@ -306,6 +340,14 @@  typedef struct _MEMORY{
     UINT32          Config2;
 }MEMORY;
 
+typedef struct _NUMAINFO{
+    UINT8           NodeId;
+    UINT64          Base;
+    UINT64          Length;
+    UINT32          DieInterleaveEn;
+}NUMAINFO;
+
+
 typedef struct _GBL_DATA
 {
     DDR_CHANNEL Channel[MAX_SOCKET][MAX_CHANNEL];
@@ -319,6 +361,7 @@  typedef struct _GBL_DATA
     UINT32      SpdTck;
     UINT32      Tck;
     UINT32      DdrFreqIdx;
+    UINT32      DevParaFreqIdx;
     UINT32      MemSize;
     UINT32      EccEn;
 
@@ -365,6 +408,7 @@  typedef struct _GBL_DATA
     BOOLEAN     chipIsEc;
     NVRAM       nvram;
     MEMORY      mem;
+    NUMAINFO    NumaInfo[MAX_NODE_TYPE][MAX_NUM_PER_TYPE];
 
 }GBL_DATA, *pGBL_DATA;
 
diff --git a/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h b/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h
index f374112..23e1393 100644
--- a/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h
+++ b/Chips/Hisilicon/Include/Library/PlatformSysCtrlLib.h
@@ -90,8 +90,14 @@  VOID DResetUsb ();
 UINT32 PlatformGetEhciBase ();
 UINT32 PlatformGetOhciBase ();
 VOID PlatformPllInit();
+VOID SiclPllInit(UINT32 SclId);
 VOID PlatformDeviceDReset();
 VOID PlatformGicdInit();
 VOID PlatformLpcInit();
+VOID PlatformArchTimerSynchronize();
+VOID PlatformEventBroadcastConfig();
+UINTN GetDjtagRegBase(UINT32 NodeId);
+VOID LlcCleanInvalidateAsm();
+VOID PlatformMdioInit();
 
 #endif
diff --git a/Chips/Hisilicon/Include/PlatformArch.h b/Chips/Hisilicon/Include/PlatformArch.h
index f1ccbb6..b34f62f 100644
--- a/Chips/Hisilicon/Include/PlatformArch.h
+++ b/Chips/Hisilicon/Include/PlatformArch.h
@@ -26,6 +26,8 @@ 
 #define MAX_DIMM        3
 #define MAX_RANK_CH     12
 #define MAX_RANK_DIMM   4
+#define MAX_NODE_TYPE   4
+#define MAX_NUM_PER_TYPE 8
 
 #define S1_BASE               0x40000000000