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[209.132.180.67]) by mx.google.com with ESMTP id d9si10824790pgg.140.2016.10.14.04.39.42; Fri, 14 Oct 2016 04:39:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754399AbcJNLjj (ORCPT + 4 others); Fri, 14 Oct 2016 07:39:39 -0400 Received: from mail-qt0-f175.google.com ([209.85.216.175]:34985 "EHLO mail-qt0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754385AbcJNLjh (ORCPT ); Fri, 14 Oct 2016 07:39:37 -0400 Received: by mail-qt0-f175.google.com with SMTP id f6so74463028qtd.2 for ; Fri, 14 Oct 2016 04:39:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=R2vdExRANhUPDQjmmWwPlWtkw1SCpO6WJ/2K6l7AsZM=; b=agn30sJoQ/r+c+0XIdgXgGV4LpL+qthwGprQIq+UBKIMCFxEaAfuN8BXsLKnrr6q0v Oc9uPq0Abto83tyQMw4jSboxXkZ8EVu1uvRVWNNRMVOguvHqPAQ277bipSvi1fJo5vpd 8FTBBrVB3JcOgtCrfMn2WMt0DMXB4A5lw5LWw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=R2vdExRANhUPDQjmmWwPlWtkw1SCpO6WJ/2K6l7AsZM=; b=U5t96uq0zNqT08ObSgqTXOZlKW7zbHsKjKxtQVMLvOASSM+WrphPTwVJqNoLP1pPRZ 77bT0QvYYSPdEbLdLMmG2KEBqvTGFcYmTjKm76ZwRpU0p5tzMGTTy2Xk7yhbEcDttgDN hTIeL8EnCOQ4pHpy6lPeY4MsFblrmVb+TMdWBXDLaZRmYasBnpCC9rxopVy2KTH+8Du/ xI5SBZ1rMU6A/l37yEclC5ceKui+TChfyUKTmQ7E7m8VA77enprfJhJYNQOM5LSL/Qc6 mTCP/9TZp/qwVraTOd2zL4jw61VxxZGyU3paqsXfY8+Km1gz5emgOuLVtTpPW9A3y2aD YVDw== X-Gm-Message-State: AA6/9RkQ8zqg5iq7sjwSZXlL5yFbtoe7F9KoQhaxh/+6y8j6oaNI4aPR/c40yC5USmfq9Usm X-Received: by 10.28.59.212 with SMTP id i203mr1313513wma.81.1476445176387; Fri, 14 Oct 2016 04:39:36 -0700 (PDT) Received: from localhost.localdomain ([105.149.88.69]) by smtp.gmail.com with ESMTPSA id qo8sm31177966wjc.46.2016.10.14.04.39.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 14 Oct 2016 04:39:35 -0700 (PDT) From: Ard Biesheuvel To: romieu@fr.zoreil.com, nic_swsd@realtek.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, davem@davemloft.net Cc: Ard Biesheuvel Subject: [PATCH] r8169: set coherent DMA mask as well as streaming DMA mask Date: Fri, 14 Oct 2016 12:39:30 +0100 Message-Id: <1476445170-4496-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org PCI devices that are 64-bit DMA capable should set the coherent DMA mask as well as the streaming DMA mask. On some architectures, these are managed separately, and so the coherent DMA mask will be left at its default value of 32 if it is not set explicitly. This results in errors such as r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded hwdev DMA mask = 0x00000000ffffffff, dev_addr = 0x00000080fbfff000 swiotlb: coherent allocation failed for device 0000:02:00.0 size=4096 CPU: 0 PID: 1062 Comm: systemd-udevd Not tainted 4.8.0+ #35 Hardware name: AMD Seattle/Seattle, BIOS 10:53:24 Oct 13 2016 on systems without memory that is 32-bit addressable by PCI devices. Signed-off-by: Ard Biesheuvel --- drivers/net/ethernet/realtek/r8169.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c index e55638c7505a..04957a36b11f 100644 --- a/drivers/net/ethernet/realtek/r8169.c +++ b/drivers/net/ethernet/realtek/r8169.c @@ -8273,7 +8273,8 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) if ((sizeof(dma_addr_t) > 4) && (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) && tp->mac_version >= RTL_GIGA_MAC_VER_18)) && - !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { + !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && + !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */ if (!pci_is_pcie(pdev)) @@ -8281,6 +8282,8 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) dev->features |= NETIF_F_HIGHDMA; } else { rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + if (!rc) + rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); if (rc < 0) { netif_err(tp, probe, dev, "DMA configuration failed\n"); goto err_out_unmap_4;