From patchwork Sun Oct 16 15:42:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 77700 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp26205qge; Sun, 16 Oct 2016 08:43:38 -0700 (PDT) X-Received: by 10.98.66.77 with SMTP id p74mr32218018pfa.15.1476632618570; Sun, 16 Oct 2016 08:43:38 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g23si23497827pgn.73.2016.10.16.08.43.38; Sun, 16 Oct 2016 08:43:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756009AbcJPPng (ORCPT + 7 others); Sun, 16 Oct 2016 11:43:36 -0400 Received: from conuserg-08.nifty.com ([210.131.2.75]:61509 "EHLO conuserg-08.nifty.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755177AbcJPPng (ORCPT ); Sun, 16 Oct 2016 11:43:36 -0400 Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-08.nifty.com with ESMTP id u9GFgiMk011014; Mon, 17 Oct 2016 00:42:47 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-08.nifty.com u9GFgiMk011014 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1476632568; bh=7fNgrSu5Iy+MUCIrARvtSEs/j/Q9keW1v5hPqVlBhNE=; h=From:To:Cc:Subject:Date:From; b=om5YxSRde27wKoQTjREbb6BcHi8P/broyuSozUdNuTD2i776MwkpBZtF4TRURTEia naefcUCFXFtebGaCZhXrI7e9k5cZ56xz9gsUBvDKbgxrUsWcPoDE7lDn4JSp94JkrA 6xuL9Crv719tOG4axk1+fHmXN71bdtCRY9BS0zkC5z2rm+gvH3NwtVL8WrkIZJwSkM RBLTILLd0tdT+ZKRBC7MTSV5LU6d0H9XPpPmYdMZ+jODVhN7G/FI9rtTUeUWN8vxiY a1eBw3EAfEsFWw7exYM18/APvcPiAnOcM2Z8ztRnVNswZ85958IvnEX19/DzUNvfMU /Uz9zVKdlXvbA== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: linux-arm-kernel@lists.infradead.org Cc: Masahiro Yamada , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Will Deacon , Mark Rutland , Catalin Marinas Subject: [PATCH 1/2] arm64: dts: uniphier: increase register region size of sysctrl node Date: Mon, 17 Oct 2016 00:42:42 +0900 Message-Id: <1476632563-7446-1-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The System Control node has 0x10000 byte of registers. The current reg size must be expanded to use the cpufreq driver because the registers controlling CPU frequency are located at offset 0x8000. Signed-off-by: Masahiro Yamada --- arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 2 +- arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 3eb4c42..da3cdd8 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -320,7 +320,7 @@ sysctrl@61840000 { compatible = "socionext,uniphier-ld11-sysctrl", "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; + reg = <0x61840000 0x10000>; sys_clk: clock { compatible = "socionext,uniphier-ld11-clock"; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 08fd7cf..efb47ea 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -311,7 +311,7 @@ sysctrl@61840000 { compatible = "socionext,uniphier-sysctrl", "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; + reg = <0x61840000 0x10000>; sys_clk: clock { compatible = "socionext,uniphier-ld20-clock";