[21/41] target/sparc: Implement FPADD64 FPSUB64

Message ID	20240302051601.53649-22-richard.henderson@linaro.org
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Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 21/41] target/sparc: Implement FPADD64 FPSUB64 Date: Fri, 1 Mar 2024 19:15:41 -1000 Message-Id: <20240302051601.53649-22-richard.henderson@linaro.org> In-Reply-To: <20240302051601.53649-1-richard.henderson@linaro.org> References: <20240302051601.53649-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	target/sparc: Implement VIS4 \| expand [00/41] target/sparc: Implement VIS4 [01/41] linux-user/sparc: Add more hwcap bits for sparc64 [02/41] target/sparc: Fix FEXPAND [03/41] target/sparc: Fix FMUL8x16 [04/41] target/sparc: Fix FMUL8x16A{U,L} [05/41] target/sparc: Fix FMULD8*X16 [06/41] target/sparc: Fix FPMERGE [07/41] target/sparc: Split out do_ms16b [08/41] target/sparc: Perform DFPREG/QFPREG in decodetree [09/41] target/sparc: Remove gen_dest_fpr_D [10/41] target/sparc: Remove cpu_fpr[] [11/41] target/sparc: Use gvec for VIS1 parallel add/sub [12/41] target/sparc: Implement FMAf extension [13/41] target/sparc: Add feature bits for VIS 3 [14/41] target/sparc: Implement ADDXC, ADDXCcc [15/41] target/sparc: Implement CMASK instructions [16/41] target/sparc: Implement FCHKSM16 [17/41] target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD [18/41] target/sparc: Implement FNMUL [19/41] target/sparc: Implement FLCMP [20/41] target/sparc: Implement FMEAN16 [21/41] target/sparc: Implement FPADD64 FPSUB64 [22/41] target/sparc: Implement FPADDS, FPSUBS [23/41] target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8 [24/41] target/sparc: Implement FSLL, FSRL, FSRA, FSLAS [25/41] target/sparc: Implement LDXEFSR [26/41] target/sparc: Implement LZCNT [27/41] target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd [28/41] target/sparc: Implement PDISTN [29/41] target/sparc: Implement UMULXHI [30/41] target/sparc: Implement XMULX [31/41] target/sparc: Enable VIS3 feature bit [32/41] target/sparc: Implement IMA extension [33/41] target/sparc: Add feature bit for VIS4 [34/41] target/sparc: Implement FALIGNDATAi [35/41] target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS [36/41] target/sparc: Implement VIS4 comparisons [37/41] target/sparc: Implement FPMIN, FPMAX [38/41] target/sparc: Implement SUBXC, SUBXCcc [39/41] target/sparc: Implement MWAIT [40/41] target/sparc: Implement monitor asis [41/41] target/sparc: Enable VIS4 feature bit

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20240302051601.53649-22-richard.henderson@linaro.org

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	atar4qemu@gmail.com
Subject: [PATCH 21/41] target/sparc: Implement FPADD64 FPSUB64
Date: Fri,  1 Mar 2024 19:15:41 -1000
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Series

target/sparc: Implement VIS4 | expand

Commit Message

Richard Henderson March 2, 2024, 5:15 a.m. UTC

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/translate.c  | 3 +++
 target/sparc/insns.decode | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 4876d46ebb..9af30d8fa7 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4905,6 +4905,9 @@  TRANS(FHSUBd, VIS3, do_ddd, a, gen_op_fhsubd)
 TRANS(FNHADDd, VIS3, do_ddd, a, gen_op_fnhaddd)
 TRANS(FNADDd, VIS3, do_ddd, a, gen_op_fnaddd)
 
+TRANS(FPADD64, VIS3B, do_ddd, a, tcg_gen_add_i64)
+TRANS(FPSUB64, VIS3B, do_ddd, a, tcg_gen_sub_i64)
+
 static bool do_rdd(DisasContext *dc, arg_r_r_r *a,
                    void (*func)(TCGv, TCGv_i64, TCGv_i64))
 {
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index bc5640aa5f..c9dab4236d 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -441,10 +441,12 @@  FCMPEq      10 000 cc:2 110101 .....  0 0101 0111 .....    \
     FPADD16s    10 ..... 110110 ..... 0 0101 0001 .....    @r_r_r
     FPADD32     10 ..... 110110 ..... 0 0101 0010 .....    @d_d_d
     FPADD32s    10 ..... 110110 ..... 0 0101 0011 .....    @r_r_r
+    FPADD64     10 ..... 110110 ..... 0 0100 0010 .....    @d_d_d
     FPSUB16     10 ..... 110110 ..... 0 0101 0100 .....    @d_d_d
     FPSUB16s    10 ..... 110110 ..... 0 0101 0101 .....    @r_r_r
     FPSUB32     10 ..... 110110 ..... 0 0101 0110 .....    @d_d_d
     FPSUB32s    10 ..... 110110 ..... 0 0101 0111 .....    @r_r_r
+    FPSUB64     10 ..... 110110 ..... 0 0100 0110 .....    @d_d_d
 
     FNORd       10 ..... 110110 ..... 0 0110 0010 .....    @d_d_d
     FNORs       10 ..... 110110 ..... 0 0110 0011 .....    @r_r_r

[21/41] target/sparc: Implement FPADD64 FPSUB64

Commit Message

Patch