diff mbox

[Linaro-uefi,v2,09/24] Hisilicon/PCIeInit: Remove unused function PciePortReset

Message ID 1476796207-94336-10-git-send-email-heyi.guo@linaro.org
State Superseded
Headers show

Commit Message

gary guo Oct. 18, 2016, 1:09 p.m. UTC 
The PciePortReset function is unuesed, so we remove it.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
 .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c      | 38 ----------------------
 1 file changed, 38 deletions(-)

Comments

Leif Lindholm Oct. 27, 2016, 2:10 p.m. UTC | #1 
On Tue, Oct 18, 2016 at 09:09:53PM +0800, Heyi Guo wrote:
> The PciePortReset function is unuesed, so we remove it.

unuesed -> unused
If you fix that for v3:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
> ---
>  .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c      | 38 ----------------------
>  1 file changed, 38 deletions(-)
> 
> diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
> index fa48a6e..85fd319 100644
> --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
> +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
> @@ -584,44 +584,6 @@ VOID PcieEqualization(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
>  }
>  
>  
> -EFI_STATUS PciePortReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
> -{
> -    if(Port >= PCIE_MAX_PORT_NUM)
> -    {
> -        return EFI_INVALID_PARAMETER;
> -    }
> -
> -
> -    if(PcieIsLinkUp(soctype, HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port])
> -    {
> -        (VOID)PcieDisableItssm(soctype, HostBridgeNum, Port);
> -    }
> -
> -    mPcieIntCfg.PortIsInitilized[Port] = FALSE;
> -    mPcieIntCfg.DmaResource[Port] = (VOID *)NULL;
> -    mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0;
> -    mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0;
> -    ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U));
> -
> -    if(Port <= 2)
> -    {
> -        RegWrite(pcie_subctrl_base[HostBridgeNum]+ PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1);
> -        MicroSecondDelay(0x1000);
> -
> -        RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1);
> -        MicroSecondDelay(0x1000);
> -    }
> -    else
> -    {
> -        RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1);
> -        MicroSecondDelay(0x1000);
> -
> -        RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1);
> -        MicroSecondDelay(0x1000);
> -    }
> -    return EFI_SUCCESS;
> -}
> -
>  EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
>  {
>      UINT32 PortIndexInSicl;
> -- 
> 1.9.1
>
diff mbox

Patch

diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
index fa48a6e..85fd319 100644
--- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
+++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
@@ -584,44 +584,6 @@  VOID PcieEqualization(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
 }
 
 
-EFI_STATUS PciePortReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
-{
-    if(Port >= PCIE_MAX_PORT_NUM)
-    {
-        return EFI_INVALID_PARAMETER;
-    }
-
-
-    if(PcieIsLinkUp(soctype, HostBridgeNum, Port) && mPcieIntCfg.PortIsInitilized[Port])
-    {
-        (VOID)PcieDisableItssm(soctype, HostBridgeNum, Port);
-    }
-
-    mPcieIntCfg.PortIsInitilized[Port] = FALSE;
-    mPcieIntCfg.DmaResource[Port] = (VOID *)NULL;
-    mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_READ] = 0;
-    mPcieIntCfg.DmaChannel[Port][PCIE_DMA_CHANLE_WRITE] = 0;
-    ZeroMem(&mPcieIntCfg.Dev[Port], sizeof(DRIVER_CFG_U));
-
-    if(Port <= 2)
-    {
-        RegWrite(pcie_subctrl_base[HostBridgeNum]+ PCIE_SUBCTRL_SC_PCIE0_RESET_REQ_REG + (UINT32)(8 * Port), 0x1);
-        MicroSecondDelay(0x1000);
-
-        RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE0_RESET_DREQ_REG + (UINT32)(8 * Port), 0x1);
-        MicroSecondDelay(0x1000);
-    }
-    else
-    {
-        RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_REQ_REG,0x1);
-        MicroSecondDelay(0x1000);
-
-        RegWrite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE3_RESET_DREQ_REG,0x1);
-        MicroSecondDelay(0x1000);
-    }
-    return EFI_SUCCESS;
-}
-
 EFI_STATUS AssertPcieCoreReset(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
 {
     UINT32 PortIndexInSicl;