[Linaro-uefi,v2,10/24] Hisilicon/PCIeInit: fix PciePcsInit bug

Message ID 1476796207-94336-11-git-send-email-heyi.guo@linaro.org
State New
Headers show

Commit Message

gary guo Oct. 18, 2016, 1:09 p.m.
There are 8 phys at each Pcie Controller, so it should be set
for 8 times loop.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
 Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

Comments

Leif Lindholm Oct. 27, 2016, 2:13 p.m. | #1
On Tue, Oct 18, 2016 at 09:09:54PM +0800, Heyi Guo wrote:
> There are 8 phys at each Pcie Controller, so it should be set
> for 8 times loop.

Should this (once review complete) be squashed into one of the
previous commits?

> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
> ---
>  Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
> index 85fd319..98ce77b 100644
> --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
> +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
> @@ -477,9 +477,12 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
>      UINT32 Value = 0;
>      if (0x1610 == soctype)
>      {
> -        RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
> -        Value |= (1 << 20);
> -        RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
> +        for (i = 0; i < 8; i++)

Could there be a Pcd or a #define for that '8'?

> +        {

Move '{' for for line.

> +            RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value);

Could we have #define for that 0x204, and preferably the 0x4?

> +            Value |= (1 << 20);
> +            RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value);
> +        }
>          PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0);
>          RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090);
>      }
> -- 
> 1.9.1
>

Patch

diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
index 85fd319..98ce77b 100644
--- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
+++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c
@@ -477,9 +477,12 @@  VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port)
     UINT32 Value = 0;
     if (0x1610 == soctype)
     {
-        RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
-        Value |= (1 << 20);
-        RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value);
+        for (i = 0; i < 8; i++)
+        {
+            RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value);
+            Value |= (1 << 20);
+            RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value);
+        }
         PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0);
         RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090);
     }