From patchwork Tue Oct 18 13:09:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 78020 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp880027qge; Tue, 18 Oct 2016 06:15:39 -0700 (PDT) X-Received: by 10.200.42.201 with SMTP id c9mr414125qta.121.1476796539901; Tue, 18 Oct 2016 06:15:39 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id 87si1809053qkx.331.2016.10.18.06.15.39; Tue, 18 Oct 2016 06:15:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 7A74D60862; Tue, 18 Oct 2016 13:15:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 5856A60B2A; Tue, 18 Oct 2016 13:12:41 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 0E62C60DCB; Tue, 18 Oct 2016 13:12:11 +0000 (UTC) Received: from mail-pf0-f172.google.com (mail-pf0-f172.google.com [209.85.192.172]) by lists.linaro.org (Postfix) with ESMTPS id C711160D5A for ; Tue, 18 Oct 2016 13:11:42 +0000 (UTC) Received: by mail-pf0-f172.google.com with SMTP id s8so94688023pfj.2 for ; Tue, 18 Oct 2016 06:11:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RuWg0AXI8aLEy5JaR2pS1OmaUbP+4+NM1BmiMk5ZDAY=; b=RQvAd2oQwxyCey/AwR+hSjB4ijUdLG9VHTHezxNNiULjUSek22uX+Hh+mkXKyWJDFL Ej4iWGb18L/eMEfIsGLqzb3SYDVtoYszA5dISUtRvJXip7NZaH1Gsz5kRwHYhy2Zy1YO v2XhoVOEPMeQvwvO6zN6TIvL2ic8MbfD9Ob6Ve+ypCTyqhoMoF6VTlzg9kz7Km+e0q7B YrDzvK6fF2OMVd7cHvSfy3SI8dmSfQ6vvflMjSZwlIAOC0PLDd993icQXZXbanXeMYzT Zwcn4YbbUf2O69OVTzu8b6+eszvFA4sbtl6AzNur7N1QXZ5fvfBWd4qcwRVnHGcFnqPa Hagg== X-Gm-Message-State: AA6/9RkimWCHUnkZBAgkF2UnPt2f6sLNeU4FoyZMhbgt9xo5EbVQZN2GtkdRMCjntKUGkXbkwz4= X-Received: by 10.98.68.7 with SMTP id r7mr594092pfa.77.1476796302151; Tue, 18 Oct 2016 06:11:42 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id a88sm56088460pfe.21.2016.10.18.06.11.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Oct 2016 06:11:41 -0700 (PDT) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Tue, 18 Oct 2016 21:09:54 +0800 Message-Id: <1476796207-94336-11-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476796207-94336-1-git-send-email-heyi.guo@linaro.org> References: <1476796207-94336-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [PATCH v2 10/24] Hisilicon/PCIeInit: fix PciePcsInit bug X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" There are 8 phys at each Pcie Controller, so it should be set for 8 times loop. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo --- Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 85fd319..98ce77b 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -477,9 +477,12 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) UINT32 Value = 0; if (0x1610 == soctype) { - RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value); - Value |= (1 << 20); - RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i*0x4, Value); + for (i = 0; i < 8; i++) + { + RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value); + Value |= (1 << 20); + RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x204 + i * 0x4, Value); + } PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0); RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090); }