| Message ID | 1476840686-94794-2-git-send-email-heyi.guo@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
Sorry there was something wrong when sending the patches at the first time (incorrect "From: " field in the 2 formatted patches), so I just send them again separately. Regards, Heyi 在 10/19/2016 9:31 AM, Heyi Guo 写道: > Modify OemGetSerdesParam interface to support D05, for it has 2 sockets > on the board, and each socket has 2 IO super clusters. The interface > is modified to support getting serdes parameter for both IO super clusters > (denoted as A and B) on each socket. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Peicong Li <lipeicong@huawei.com> > --- > .../Type09/MiscSystemSlotDesignationFunction.c | 15 ++++++++------- > Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 2 +- > Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h | 2 +- > .../Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c | 8 ++++---- > .../D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c | 6 +++--- > 5 files changed, 17 insertions(+), 16 deletions(-) > > diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c > index a0e3de3..bc988d8 100644 > --- a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c > +++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c > @@ -73,9 +73,10 @@ UpdateSlotUsage( > ) > { > EFI_STATUS Status; > - serdes_param_t sSerdesParam; > + serdes_param_t SerdesParamA; > + serdes_param_t SerdesParamB; > > - Status = OemGetSerdesParam (&sSerdesParam); > + Status = OemGetSerdesParam (&SerdesParamA, &SerdesParamB, 0); > if(EFI_ERROR(Status)) > { > DEBUG((EFI_D_ERROR, "[%a]:[%dL] OemGetSerdesParam failed %r\n", __FUNCTION__, __LINE__, Status)); > @@ -85,7 +86,7 @@ UpdateSlotUsage( > // > // PCIE0 > // > - if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data) && sSerdesParam.hilink1_mode == EM_HILINK1_PCIE0_8LANE) > + if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data) && SerdesParamA.hilink1_mode == EM_HILINK1_PCIE0_8LANE) > { > InputData->CurrentUsage = SlotUsageAvailable; > } > @@ -95,7 +96,7 @@ UpdateSlotUsage( > // > if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie1Data) > { > - if (sSerdesParam.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) > + if (SerdesParamA.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) > { > InputData->SlotDataBusWidth = SlotDataBusWidth4X; > } > @@ -106,12 +107,12 @@ UpdateSlotUsage( > // > if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie2Data) > { > - if (sSerdesParam.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) > + if (SerdesParamA.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) > { > InputData->SlotDataBusWidth = SlotDataBusWidth4X; > InputData->CurrentUsage = SlotUsageAvailable; > } > - else if (sSerdesParam.hilink2_mode == EM_HILINK2_PCIE2_8LANE) > + else if (SerdesParamA.hilink2_mode == EM_HILINK2_PCIE2_8LANE) > { > InputData->CurrentUsage = SlotUsageAvailable; > } > @@ -120,7 +121,7 @@ UpdateSlotUsage( > // > // PCIE3 > // > - if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data) && sSerdesParam.hilink5_mode == EM_HILINK5_PCIE3_4LANE) > + if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data) && SerdesParamA.hilink5_mode == EM_HILINK5_PCIE3_4LANE) > { > InputData->CurrentUsage = SlotUsageAvailable; > } > diff --git a/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h > index 700d40e..3bd5a0f 100755 > --- a/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h > +++ b/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h > @@ -82,7 +82,7 @@ typedef struct { > UINT32 DsCfg; > } SERDES_POLARITY_INVERT; > > -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param); > +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); > extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; > extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; > UINT32 GetEthType(UINT8 EthChannel); > diff --git a/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h > index 070934b..b6c7e20 100644 > --- a/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h > +++ b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h > @@ -76,7 +76,7 @@ typedef struct { > } SERDES_POLARITY_INVERT; > > > -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param); > +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); > extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; > extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; > UINT32 GetEthType(UINT8 EthChannel); > diff --git a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c > index d4aa84a..2dc1464 100644 > --- a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c > +++ b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c > @@ -59,15 +59,15 @@ serdes_param_t gSerdesParam = { > .hilink5_mode = EM_HILINK5_SAS1_4LANE, > }; > > -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param) > +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId) > { > - if (NULL == Param) > + if (ParamA == NULL) > { > - DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__)); > + DEBUG((EFI_D_ERROR, "[%a]:[%dL] ParamA == NULL!\n", __FUNCTION__, __LINE__)); > return EFI_INVALID_PARAMETER; > } > > - (VOID) CopyMem(Param, &gSerdesParam, sizeof(*Param)); > + (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA)); > return EFI_SUCCESS; > } > > diff --git a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c > index 23c55e1..7e4b9d0 100644 > --- a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c > +++ b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c > @@ -75,15 +75,15 @@ serdes_param_t gSerdesParam1 = { > .use_ssc = 0, > }; > > -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param) > +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId) > { > - if (NULL == Param) > + if (ParamA == NULL) > { > DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__)); > return EFI_INVALID_PARAMETER; > } > > - (VOID) CopyMem(Param, &gSerdesParam, sizeof(*Param)); > + (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA)); > return EFI_SUCCESS; > } >
diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c index a0e3de3..bc988d8 100644 --- a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c +++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c @@ -73,9 +73,10 @@ UpdateSlotUsage( ) { EFI_STATUS Status; - serdes_param_t sSerdesParam; + serdes_param_t SerdesParamA; + serdes_param_t SerdesParamB; - Status = OemGetSerdesParam (&sSerdesParam); + Status = OemGetSerdesParam (&SerdesParamA, &SerdesParamB, 0); if(EFI_ERROR(Status)) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] OemGetSerdesParam failed %r\n", __FUNCTION__, __LINE__, Status)); @@ -85,7 +86,7 @@ UpdateSlotUsage( // // PCIE0 // - if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data) && sSerdesParam.hilink1_mode == EM_HILINK1_PCIE0_8LANE) + if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data) && SerdesParamA.hilink1_mode == EM_HILINK1_PCIE0_8LANE) { InputData->CurrentUsage = SlotUsageAvailable; } @@ -95,7 +96,7 @@ UpdateSlotUsage( // if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie1Data) { - if (sSerdesParam.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) + if (SerdesParamA.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) { InputData->SlotDataBusWidth = SlotDataBusWidth4X; } @@ -106,12 +107,12 @@ UpdateSlotUsage( // if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie2Data) { - if (sSerdesParam.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) + if (SerdesParamA.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) { InputData->SlotDataBusWidth = SlotDataBusWidth4X; InputData->CurrentUsage = SlotUsageAvailable; } - else if (sSerdesParam.hilink2_mode == EM_HILINK2_PCIE2_8LANE) + else if (SerdesParamA.hilink2_mode == EM_HILINK2_PCIE2_8LANE) { InputData->CurrentUsage = SlotUsageAvailable; } @@ -120,7 +121,7 @@ UpdateSlotUsage( // // PCIE3 // - if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data) && sSerdesParam.hilink5_mode == EM_HILINK5_PCIE3_4LANE) + if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data) && SerdesParamA.hilink5_mode == EM_HILINK5_PCIE3_4LANE) { InputData->CurrentUsage = SlotUsageAvailable; } diff --git a/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h index 700d40e..3bd5a0f 100755 --- a/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h +++ b/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h @@ -82,7 +82,7 @@ typedef struct { UINT32 DsCfg; } SERDES_POLARITY_INVERT; -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param); +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; UINT32 GetEthType(UINT8 EthChannel); diff --git a/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h index 070934b..b6c7e20 100644 --- a/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h +++ b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h @@ -76,7 +76,7 @@ typedef struct { } SERDES_POLARITY_INVERT; -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param); +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; UINT32 GetEthType(UINT8 EthChannel); diff --git a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c index d4aa84a..2dc1464 100644 --- a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c +++ b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c @@ -59,15 +59,15 @@ serdes_param_t gSerdesParam = { .hilink5_mode = EM_HILINK5_SAS1_4LANE, }; -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param) +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId) { - if (NULL == Param) + if (ParamA == NULL) { - DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__)); + DEBUG((EFI_D_ERROR, "[%a]:[%dL] ParamA == NULL!\n", __FUNCTION__, __LINE__)); return EFI_INVALID_PARAMETER; } - (VOID) CopyMem(Param, &gSerdesParam, sizeof(*Param)); + (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA)); return EFI_SUCCESS; } diff --git a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c index 23c55e1..7e4b9d0 100644 --- a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c +++ b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c @@ -75,15 +75,15 @@ serdes_param_t gSerdesParam1 = { .use_ssc = 0, }; -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param) +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId) { - if (NULL == Param) + if (ParamA == NULL) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__)); return EFI_INVALID_PARAMETER; } - (VOID) CopyMem(Param, &gSerdesParam, sizeof(*Param)); + (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA)); return EFI_SUCCESS; }
Modify OemGetSerdesParam interface to support D05, for it has 2 sockets on the board, and each socket has 2 IO super clusters. The interface is modified to support getting serdes parameter for both IO super clusters (denoted as A and B) on each socket. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Peicong Li <lipeicong@huawei.com> --- .../Type09/MiscSystemSlotDesignationFunction.c | 15 ++++++++------- Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 2 +- Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h | 2 +- .../Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c | 8 ++++---- .../D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c | 6 +++--- 5 files changed, 17 insertions(+), 16 deletions(-)