From patchwork Tue Oct 25 09:06:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 79138 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp3003052qge; Tue, 25 Oct 2016 02:06:24 -0700 (PDT) X-Received: by 10.98.99.2 with SMTP id x2mr37388223pfb.136.1477386384244; Tue, 25 Oct 2016 02:06:24 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h190si19707964pgc.72.2016.10.25.02.06.24; Tue, 25 Oct 2016 02:06:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756133AbcJYJGX (ORCPT + 3 others); Tue, 25 Oct 2016 05:06:23 -0400 Received: from mail-lf0-f52.google.com ([209.85.215.52]:37222 "EHLO mail-lf0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932827AbcJYJGT (ORCPT ); Tue, 25 Oct 2016 05:06:19 -0400 Received: by mail-lf0-f52.google.com with SMTP id m193so10711108lfm.4 for ; Tue, 25 Oct 2016 02:06:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JeKUGtTf2XKfiSC2fhhxwMY1MFB4V9Kivd92cK8nnNc=; b=BSdJYs4B/rvdG5WiMgdN8zX28Ddu48iCOsmdnB9vdVjboWQSZNEQ3rqlD3I8j2vf2Y iZn0m4HZDfLxp+dw27Kyx/AAXsQpfyCmIk6ot5olmw7NzWZZr4yQKzh81RU9hGIWp6ei xoYDrSLsw0HM+hViyR5Ds74pcULMYJkhWpLBI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JeKUGtTf2XKfiSC2fhhxwMY1MFB4V9Kivd92cK8nnNc=; b=RO9Ja+Lk/TKqNGqL4or3e/ceSZR/8/6usGaT/kn+AMIPrg+PkyDsrq8hvzIE+zudTG wpM1TPvFVqP8PilGXr/RJVP4XWpHNlPp7Fu/8l0fPTgGu72CgdmpiwGDxDCz3aJYuf2X nlqxHzetVBQ3QWdIhZfWUeVZj/piRHkEiySemWq3WmPoIiOzkmsyAH4F3oLf/jjGpXv2 ul7itWgwe83CrweoGXePCSgCxXvtoaI/bODiAlurnV48rscp7SCfzK5479uE0ze3KRae 2c/svxkKfzYOuWJZCJJHrH8WGq5tOKQuZbgxaVUUYa4KjWmTBszh0Qk9MMf0eMazI4Yd 0PMw== X-Gm-Message-State: ABUngvdxfma+oV4zmH6TxUo2AWQNlgqhENhLP95QDdPPvjcCvE7xd9tWWqYnfqybNUNWHPlb X-Received: by 10.25.22.207 with SMTP id 76mr164370lfw.128.1477386377277; Tue, 25 Oct 2016 02:06:17 -0700 (PDT) Received: from linuslaptop.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id h67sm3736309lji.29.2016.10.25.02.06.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 25 Oct 2016 02:06:16 -0700 (PDT) From: Linus Walleij To: Ulf Hansson , linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Srinivas Kandagatla Cc: Russell King , Linus Walleij Subject: [PATCH 3/3 v2] RFC: mmc: mmci: add qcom specific program end support Date: Tue, 25 Oct 2016 11:06:07 +0200 Message-Id: <1477386367-18514-3-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1477386367-18514-1-git-send-email-linus.walleij@linaro.org> References: <1477386367-18514-1-git-send-email-linus.walleij@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Srinivas Kandagatla This patch adds support to programend interrupt which is very specific to QCOM integration. This interrupt is use as busy signal when a command forces the card to enter into programming state like CMD6 writing to ext_csd registers. Hopefully, this also fixes the __mmc_switch timeout issue reproted with latest versions of the eMMC used on DB600c board. This patch is based on a WIP patch from Srinivas Kandagatla and augmented by Linus Walleij for another approach. Signed-off-by: Srinivas Kandagatla Signed-off-by: Linus Walleij --- ChangeLog v1->v2: - Rebase on new register naming. Srinivas: please test to see if this fixes your problems. Sadly it does *NOT* solve my APQ8060 issues, but it would be nice if the common code path works for the busy detection on your DB600c. --- drivers/mmc/host/mmci.c | 21 +++++++++++++++++++-- drivers/mmc/host/mmci.h | 6 ++++++ 2 files changed, 25 insertions(+), 2 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 7f68fa7a961e..580ca89d33dc 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -72,7 +72,10 @@ static unsigned int fmax = 515633; * @signal_direction: input/out direction of bus signals can be indicated * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock * @busy_detect: true if the variant supports busy detection on DAT0. - * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM + * @busy_cpsm_flag: bitmask enabling busy detection in the CPSM (command + * path state machine) + * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM (data path + * state machine) * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register * indicating that the card is busy * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for @@ -103,6 +106,7 @@ struct variant_data { bool signal_direction; bool pwrreg_clkgate; bool busy_detect; + u32 busy_cpsm_flag; u32 busy_dpsm_flag; u32 busy_detect_flag; u32 busy_detect_mask; @@ -229,6 +233,10 @@ static struct variant_data variant_qcom = { .datalength_bits = 24, .pwrreg_powerup = MCI_PWR_UP, .f_max = 208000000, + .busy_detect = true, + .busy_cpsm_flag = MCI_CPSM_QCOM_PROGENA, + .busy_detect_flag = MCI_QCOM_PROGDONE, + .busy_detect_mask = MCI_QCOM_PROGDONEMASK, .explicit_mclk_control = true, .qcom_fifo = true, .qcom_dml = true, @@ -903,6 +911,15 @@ mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) if (/*interrupt*/0) c |= MCI_CPSM_INTERRUPT; + /* + * Enable the program end interrupt for specific commands + * used for busy detection. + */ + if (host->variant->busy_detect && + (cmd->flags & MMC_RSP_R1B) == MMC_RSP_R1B) { + c |= host->variant->busy_cpsm_flag; + } + if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) c |= host->variant->data_cmd_enable; @@ -1005,7 +1022,7 @@ mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, return; /* - * ST Micro variant: handle busy detection. + * ST Micro and Qualcomm variants: handle busy detection. */ if (host->variant->busy_detect) { bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY); diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index 56322c6afba4..355259b0a24b 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -130,6 +130,8 @@ #define MCI_ST_SDIOIT (1 << 22) #define MCI_ST_CEATAEND (1 << 23) #define MCI_ST_CARDBUSY (1 << 24) +/* Extended status bits for the QCOM variants */ +#define MCI_QCOM_PROGDONE (1 << 23) #define MMCICLEAR 0x038 #define MCI_CMDCRCFAILCLR (1 << 0) @@ -147,6 +149,8 @@ #define MCI_ST_SDIOITC (1 << 22) #define MCI_ST_CEATAENDC (1 << 23) #define MCI_ST_BUSYENDC (1 << 24) +/* Extended status bits for the QCOM variants */ +#define MCI_QCOM_PROGDONECLR (1 << 23) #define MMCIMASK0 0x03c #define MCI_CMDCRCFAILMASK (1 << 0) @@ -175,6 +179,8 @@ #define MCI_ST_SDIOITMASK (1 << 22) #define MCI_ST_CEATAENDMASK (1 << 23) #define MCI_ST_BUSYENDMASK (1 << 24) +/* Extended status bits for the Qualcomm variants */ +#define MCI_QCOM_PROGDONEMASK (1 << 23) #define MMCIMASK1 0x040 #define MMCIFIFOCNT 0x048