[SPARC] Housekeeping work

Message ID	7748716.p3pH1ECX6Z@polaris
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of gcc-patches-return-439549-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=lVWQf1Xa4nOqMXRp Ox/+eYIhGaCl71XyY+HgUGMbcAyCwHhyYanYD2C271gLaBeUmS7yeJk0GtDSAVjh T8HXXn/Ba1Hv6epkBu6JUSeds93xjP+KxexDU55C8C2fYjtDnV1+7mVYoaEHCMXK azNLyOd9jPyAg4X55N0QYLy2qQM= Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org From: Eric Botcazou <ebotcazou@adacore.com> To: gcc-patches@gcc.gnu.org Subject: [SPARC] Housekeeping work Date: Tue, 25 Oct 2016 22:16:06 +0200 Message-ID: <7748716.p3pH1ECX6Z@polaris> User-Agent: KMail/4.14.10 (Linux/3.16.7-42-desktop; KDE/4.14.9; x86_64; ; ) MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="nextPart2570696.hIng7nyNIM" Content-Transfer-Encoding: 7Bit

Index: config.gcc =================================================================== --- config.gcc (revision 241437) +++ config.gcc (working copy) @@ -2783,7 +2783,7 @@ sparc*-*-solaris2*) tm_file="sparc/biarch64.h ${tm_file} ${sol2_tm_file} sparc/tso.h" case ${target} in sparc64-*-* | sparcv9-*-*) - tm_file="sparc/default-64.h ${tm_file}" + tm_file="sparc/default64.h ${tm_file}" ;; *) test x$with_cpu != x || with_cpu=v9 @@ -2806,7 +2806,7 @@ sparc64-*-rtems*) tmake_file="${tmake_file} sparc/t-sparc sparc/t-rtems-64" ;; sparc64-*-linux*) - tm_file="sparc/biarch64.h ${tm_file} dbxelf.h elfos.h sparc/sysv4.h gnu-user.h linux.h glibc-stdint.h sparc/default-64.h sparc/linux64.h sparc/tso.h" + tm_file="sparc/biarch64.h ${tm_file} dbxelf.h elfos.h sparc/sysv4.h gnu-user.h linux.h glibc-stdint.h sparc/default64.h sparc/linux64.h sparc/tso.h" extra_options="${extra_options} sparc/long-double-switch.opt" tmake_file="${tmake_file} sparc/t-sparc sparc/t-linux64" ;; Index: config/sparc/default-64.h =================================================================== --- config/sparc/default-64.h (revision 241437) +++ config/sparc/default-64.h (working copy) @@ -1,22 +0,0 @@ -/* Definitions of target machine for GCC, for bi-arch SPARC, - defaulting to 64-bit code generation. - - Copyright (C) 1999-2016 Free Software Foundation, Inc. - -This file is part of GCC. - -GCC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 3, or (at your option) -any later version. - -GCC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GCC; see the file COPYING3. If not see -<http://www.gnu.org/licenses/>. */ - -#define TARGET_64BIT_DEFAULT 1 Index: config/sparc/sparc.c =================================================================== --- config/sparc/sparc.c (revision 241437) +++ config/sparc/sparc.c (working copy) @@ -1384,13 +1384,13 @@ sparc_option_override (void) #ifndef SPARC_BI_ARCH /* Check for unsupported architecture size. */ - if (! TARGET_64BIT != DEFAULT_ARCH32_P) + if (!TARGET_64BIT != DEFAULT_ARCH32_P) error ("%s is not supported by this configuration", DEFAULT_ARCH32_P ? "-m64" : "-m32"); #endif /* We force all 64bit archs to use 128 bit long double */ - if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128) + if (TARGET_ARCH64 && !TARGET_LONG_DOUBLE_128) { error ("-mlong-double-64 not allowed with -m64"); target_flags |= MASK_LONG_DOUBLE_128; @@ -11739,7 +11739,7 @@ sparc_file_end (void) static const char * sparc_mangle_type (const_tree type) { - if (!TARGET_64BIT + if (TARGET_ARCH32 && TYPE_MAIN_VARIANT (type) == long_double_type_node && TARGET_LONG_DOUBLE_128) return "g"; Index: config/sparc/sparc.h =================================================================== --- config/sparc/sparc.h (revision 241437) +++ config/sparc/sparc.h (working copy) @@ -44,12 +44,12 @@ along with GCC; see the file COPYING3. #endif /* sparc64 */ #else #ifdef SPARC_BI_ARCH -#define TARGET_ARCH32 (! TARGET_64BIT) +#define TARGET_ARCH32 (!TARGET_64BIT) #else #define TARGET_ARCH32 (DEFAULT_ARCH32_P) #endif /* SPARC_BI_ARCH */ #endif /* IN_LIBGCC2 */ -#define TARGET_ARCH64 (! TARGET_ARCH32) +#define TARGET_ARCH64 (!TARGET_ARCH32) /* Code model selection in 64-bit environment. Index: config/sparc/sparc.md =================================================================== --- config/sparc/sparc.md (revision 241452) +++ config/sparc/sparc.md (working copy) @@ -1,8 +1,8 @@ -;; Machine description for SPARC chip for GCC -;; Copyright (C) 1987-2016 Free Software Foundation, Inc. -;; Contributed by Michael Tiemann (tiemann@cygnus.com) -;; 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, -;; at Cygnus Support. +;; Machine description for SPARC. +;; Copyright (C) 1987-2016 Free Software Foundation, Inc. +;; Contributed by Michael Tiemann (tiemann@cygnus.com) +;; 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, +;; at Cygnus Support. ;; This file is part of GCC. @@ -20,8 +20,6 @@ ;; along with GCC; see the file COPYING3. If not see ;; <http://www.gnu.org/licenses/>. -;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. - (define_c_enum "unspec" [ UNSPEC_MOVE_PIC UNSPEC_UPDATE_RETURN @@ -205,8 +203,8 @@ (define_constants (GSR_REG 102) ]) -(define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) (define_mode_iterator I [QI HI SI DI]) +(define_mode_iterator P [(SI "TARGET_ARCH32") (DI "TARGET_ARCH64")]) (define_mode_iterator W [SI (DI "TARGET_ARCH64")]) (define_mode_iterator F [SF DF TF]) @@ -710,7 +708,7 @@ (define_insn_and_split "*snedi<W:mode>_z (const_int 0)))] "TARGET_ARCH64 && !TARGET_VIS3" "#" - "&& ! reg_overlap_mentioned_p (operands[1], operands[0])" + "&& !reg_overlap_mentioned_p (operands[1], operands[0])" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:W (ne:DI (match_dup 1) (const_int 0)) (const_int 1) @@ -737,7 +735,7 @@ (define_insn_and_split "*neg_snedi<W:mod (const_int 0))))] "TARGET_ARCH64 && !TARGET_SUBXC" "#" - "&& ! reg_overlap_mentioned_p (operands[1], operands[0])" + "&& !reg_overlap_mentioned_p (operands[1], operands[0])" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:W (ne:DI (match_dup 1) (const_int 0)) (const_int -1) @@ -790,7 +788,7 @@ (define_insn_and_split "*seqdi<W:mode>_z (const_int 0)))] "TARGET_ARCH64" "#" - "&& ! reg_overlap_mentioned_p (operands[1], operands[0])" + "&& !reg_overlap_mentioned_p (operands[1], operands[0])" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:W (eq:DI (match_dup 1) (const_int 0)) (const_int 1) @@ -804,7 +802,7 @@ (define_insn_and_split "*neg_seqdi<W:mod (const_int 0))))] "TARGET_ARCH64" "#" - "&& ! reg_overlap_mentioned_p (operands[1], operands[0])" + "&& !reg_overlap_mentioned_p (operands[1], operands[0])" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:W (eq:DI (match_dup 1) (const_int 0)) (const_int -1) @@ -1220,7 +1218,7 @@ (define_insn "*subxc<W:mode>" (define_split [(set (match_operand:W 0 "register_operand" "") (match_operator:W 1 "icc_comparison_operator" - [(match_operand 2 "icc_register_operand" "") (const_int 0)]))] + [(match_operand 2 "icc_register_operand" "") (const_int 0)]))] "TARGET_V9 /* 64-bit LTU is better implemented using addxc with VIS3. */ && !(GET_CODE (operands[1]) == LTU @@ -1243,8 +1241,8 @@ (define_split (define_expand "cbranchcc4" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" - [(match_operand 1 "compare_operand" "") - (match_operand 2 "const_zero_operand" "")]) + [(match_operand 1 "compare_operand" "") + (match_operand 2 "const_zero_operand" "")]) (label_ref (match_operand 3 "" "")) (pc)))] "" @@ -1282,7 +1280,10 @@ (define_expand "cbranch<F:mode>4" (match_operand:F 2 "register_operand" "")])) (use (match_operand 3 ""))] "TARGET_FPU" - { emit_conditional_branch_insn (operands); DONE; }) +{ + emit_conditional_branch_insn (operands); + DONE; +}) ;; Now match both normal and inverted jump. @@ -1291,7 +1292,7 @@ (define_expand "cbranch<F:mode>4" (define_insn "*normal_branch" [(set (pc) (if_then_else (match_operator 0 "icc_comparison_operator" - [(reg CC_REG) (const_int 0)]) + [(reg CC_REG) (const_int 0)]) (label_ref (match_operand 1 "" "")) (pc)))] "" @@ -1307,7 +1308,7 @@ (define_insn "*normal_branch" (define_insn "*inverted_branch" [(set (pc) (if_then_else (match_operator 0 "icc_comparison_operator" - [(reg CC_REG) (const_int 0)]) + [(reg CC_REG) (const_int 0)]) (pc) (label_ref (match_operand 1 "" ""))))] "" @@ -1323,8 +1324,8 @@ (define_insn "*inverted_branch" (define_insn "*normal_fp_branch" [(set (pc) (if_then_else (match_operator 1 "comparison_operator" - [(match_operand:CCFP 0 "fcc_register_operand" "c") - (const_int 0)]) + [(match_operand:CCFP 0 "fcc_register_operand" "c") + (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "" @@ -1340,8 +1341,8 @@ (define_insn "*normal_fp_branch" (define_insn "*inverted_fp_branch" [(set (pc) (if_then_else (match_operator 1 "comparison_operator" - [(match_operand:CCFP 0 "fcc_register_operand" "c") - (const_int 0)]) + [(match_operand:CCFP 0 "fcc_register_operand" "c") + (const_int 0)]) (pc) (label_ref (match_operand 2 "" ""))))] "" @@ -1357,8 +1358,8 @@ (define_insn "*inverted_fp_branch" (define_insn "*normal_fpe_branch" [(set (pc) (if_then_else (match_operator 1 "comparison_operator" - [(match_operand:CCFPE 0 "fcc_register_operand" "c") - (const_int 0)]) + [(match_operand:CCFPE 0 "fcc_register_operand" "c") + (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "" @@ -1374,8 +1375,8 @@ (define_insn "*normal_fpe_branch" (define_insn "*inverted_fpe_branch" [(set (pc) (if_then_else (match_operator 1 "comparison_operator" - [(match_operand:CCFPE 0 "fcc_register_operand" "c") - (const_int 0)]) + [(match_operand:CCFPE 0 "fcc_register_operand" "c") + (const_int 0)]) (pc) (label_ref (match_operand 2 "" ""))))] "" @@ -1421,8 +1422,8 @@ (define_insn "*cbcond_sp64" (define_insn "*normal_int_branch_sp64" [(set (pc) (if_then_else (match_operator 0 "v9_register_comparison_operator" - [(match_operand:DI 1 "register_operand" "r") - (const_int 0)]) + [(match_operand:DI 1 "register_operand" "r") + (const_int 0)]) (label_ref (match_operand 2 "" "")) (pc)))] "TARGET_ARCH64" @@ -1437,8 +1438,8 @@ (define_insn "*normal_int_branch_sp64" (define_insn "*inverted_int_branch_sp64" [(set (pc) (if_then_else (match_operator 0 "v9_register_comparison_operator" - [(match_operand:DI 1 "register_operand" "r") - (const_int 0)]) + [(match_operand:DI 1 "register_operand" "r") + (const_int 0)]) (pc) (label_ref (match_operand 2 "" ""))))] "TARGET_ARCH64" @@ -1463,7 +1464,8 @@ (define_insn "load_pcrel_sym<P:mode>" [(set (match_operand:P 0 "register_operand" "=r") (unspec:P [(match_operand:P 1 "symbolic_operand" "") (match_operand:P 2 "call_address_operand" "") - (match_operand:P 3 "const_int_operand" "")] UNSPEC_LOAD_PCREL_SYM)) + (match_operand:P 3 "const_int_operand" "")] + UNSPEC_LOAD_PCREL_SYM)) (clobber (reg:P O7_REG))] "REGNO (operands[0]) == INTVAL (operands[3])" { @@ -1580,7 +1582,8 @@ (define_insn "*movsi_high" (define_insn "movsi_lo_sum_pic" [(set (match_operand:SI 0 "register_operand" "=r") (lo_sum:SI (match_operand:SI 1 "register_operand" "r") - (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] UNSPEC_MOVE_PIC)))] + (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] + UNSPEC_MOVE_PIC)))] "flag_pic" { #ifdef HAVE_AS_SPARC_GOTDATA_OP @@ -1606,7 +1609,8 @@ (define_insn "movsi_pic_gotdata_op" [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "register_operand" "r") - (match_operand 3 "symbolic_operand" "")] UNSPEC_MOVE_GOTDATA))] + (match_operand 3 "symbolic_operand" "")] + UNSPEC_MOVE_GOTDATA))] "flag_pic && check_pic (1)" { #ifdef HAVE_AS_SPARC_GOTDATA_OP @@ -1697,10 +1701,10 @@ (define_expand "movdi" (define_insn "*movdi_insn_sp32" [(set (match_operand:DI 0 "nonimmediate_operand" - "=T,o,T,U,o,r,r,r,?T,?*f,?*f,?o,?*e,?*e, r,?*f,?*e,?W,b,b") + "=T,o,T,U,o,r,r,r,?T,?*f,?*f,?o,?*e,?*e, r,?*f,?*e,?W,b,b") (match_operand:DI 1 "input_operand" - " J,J,U,T,r,o,i,r,*f, T, o,*f, *e, *e,?*f, r, W,*e,J,P"))] - "! TARGET_ARCH64 + " J,J,U,T,r,o,i,r,*f, T, o,*f, *e, *e,?*f, r, W,*e,J,P"))] + "TARGET_ARCH32 && (register_operand (operands[0], DImode) || register_or_zero_operand (operands[1], DImode))" "@ @@ -1800,7 +1804,8 @@ (define_insn "*movdi_lo_sum_pic_label_re (define_insn "movdi_lo_sum_pic" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") - (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] UNSPEC_MOVE_PIC)))] + (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] + UNSPEC_MOVE_PIC)))] "TARGET_ARCH64 && flag_pic" { #ifdef HAVE_AS_SPARC_GOTDATA_OP @@ -1826,7 +1831,8 @@ (define_insn "movdi_pic_gotdata_op" [(set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "register_operand" "r") - (match_operand 3 "symbolic_operand" "")] UNSPEC_MOVE_GOTDATA))] + (match_operand 3 "symbolic_operand" "")] + UNSPEC_MOVE_GOTDATA))] "TARGET_ARCH64 && flag_pic && check_pic (1)" { #ifdef HAVE_AS_SPARC_GOTDATA_OP @@ -1858,14 +1864,16 @@ (define_insn "*losum_di_medlow" (define_insn "seth44" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETH44)))] + (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] + UNSPEC_SETH44)))] "TARGET_CM_MEDMID" "sethi\t%%h44(%a1), %0") (define_insn "setm44" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") - (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_SETM44)))] + (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] + UNSPEC_SETM44)))] "TARGET_CM_MEDMID" "or\t%1, %%m44(%a2), %0") @@ -1878,20 +1886,23 @@ (define_insn "setl44" (define_insn "sethh" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETHH)))] + (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] + UNSPEC_SETHH)))] "TARGET_CM_MEDANY" "sethi\t%%hh(%a1), %0") (define_insn "setlm" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETLM)))] + (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] + UNSPEC_SETLM)))] "TARGET_CM_MEDANY" "sethi\t%%lm(%a1), %0") (define_insn "sethm" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") - (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_EMB_SETHM)))] + (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] + UNSPEC_EMB_SETHM)))] "TARGET_CM_MEDANY" "or\t%1, %%hm(%a2), %0") @@ -1904,7 +1915,8 @@ (define_insn "setlo" (define_insn "embmedany_sethi" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] UNSPEC_EMB_HISUM)))] + (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] + UNSPEC_EMB_HISUM)))] "TARGET_CM_EMBMEDANY && check_pic (1)" "sethi\t%%hi(%a1), %0") @@ -1917,26 +1929,30 @@ (define_insn "embmedany_losum" (define_insn "embmedany_brsum" [(set (match_operand:DI 0 "register_operand" "=r") - (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_EMB_HISUM))] + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_EMB_HISUM))] "TARGET_CM_EMBMEDANY" "add\t%1, %_, %0") (define_insn "embmedany_textuhi" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTUHI)))] + (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] + UNSPEC_EMB_TEXTUHI)))] "TARGET_CM_EMBMEDANY && check_pic (1)" "sethi\t%%uhi(%a1), %0") (define_insn "embmedany_texthi" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTHI)))] + (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] + UNSPEC_EMB_TEXTHI)))] "TARGET_CM_EMBMEDANY && check_pic (1)" "sethi\t%%hi(%a1), %0") (define_insn "embmedany_textulo" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") - (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] UNSPEC_EMB_TEXTULO)))] + (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] + UNSPEC_EMB_TEXTULO)))] "TARGET_CM_EMBMEDANY" "or\t%1, %%ulo(%a2), %0") @@ -1954,7 +1970,7 @@ (define_expand "reload_indi" (match_operand:TI 2 "register_operand" "=&r")])] "(TARGET_CM_MEDANY || TARGET_CM_EMBMEDANY) - && ! flag_pic" + && !flag_pic" { sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]); DONE; @@ -1966,7 +1982,7 @@ (define_expand "reload_outdi" (match_operand:TI 2 "register_operand" "=&r")])] "(TARGET_CM_MEDANY || TARGET_CM_EMBMEDANY) - && ! flag_pic" + && !flag_pic" { sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]); DONE; @@ -1976,7 +1992,7 @@ (define_expand "reload_outdi" (define_split [(set (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "const_int_operand" ""))] - "! TARGET_ARCH64 + "TARGET_ARCH32 && ((GET_CODE (operands[0]) == REG && SPARC_INT_REG_P (REGNO (operands[0]))) || (GET_CODE (operands[0]) == SUBREG @@ -1994,8 +2010,8 @@ (define_split /* Slick... but this trick loses if this subreg constant part can be done in one insn. */ if (low == high - && ! SPARC_SETHI32_P (high) - && ! SPARC_SIMM13_P (high)) + && !SPARC_SETHI32_P (high) + && !SPARC_SIMM13_P (high)) emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), gen_highpart (SImode, operands[0]))); else @@ -2008,10 +2024,9 @@ (define_split [(set (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "register_operand" ""))] "reload_completed - && (! TARGET_V9 - || (! TARGET_ARCH64 - && sparc_split_regreg_legitimate (operands[0], - operands[1])))" + && (!TARGET_V9 + || (TARGET_ARCH32 + && sparc_split_regreg_legitimate (operands[0], operands[1])))" [(clobber (const_int 0))] { rtx set_dest = operands[0]; @@ -2044,7 +2059,7 @@ (define_split (define_split [(set (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "memory_operand" ""))] - "(! TARGET_ARCH64 + "(TARGET_ARCH32 && reload_completed && sparc_splitdi_legitimate (operands[0], operands[1]))" [(clobber (const_int 0))] @@ -2070,7 +2085,7 @@ (define_split (define_split [(set (match_operand:DI 0 "memory_operand" "") (match_operand:DI 1 "register_operand" ""))] - "(! TARGET_ARCH64 + "(TARGET_ARCH32 && reload_completed && sparc_splitdi_legitimate (operands[1], operands[0]))" [(clobber (const_int 0))] @@ -2086,9 +2101,9 @@ (define_split [(set (match_operand:DI 0 "memory_operand" "") (match_operand:DI 1 "const_zero_operand" ""))] "reload_completed - && (! TARGET_V9 - || (! TARGET_ARCH64 - && ! mem_min_alignment (operands[0], 8))) + && (!TARGET_V9 + || (TARGET_ARCH32 + && !mem_min_alignment (operands[0], 8))) && offsettable_memref_p (operands[0])" [(clobber (const_int 0))] { @@ -2115,7 +2130,7 @@ (define_insn "*movti_insn_sp64" [(set (match_operand:TI 0 "nonimmediate_operand" "=r , o,?*e,?o,b") (match_operand:TI 1 "input_operand" "roJ,rJ, eo, e,J"))] "TARGET_ARCH64 - && ! TARGET_HARD_QUAD + && !TARGET_HARD_QUAD && (register_operand (operands[0], TImode) || register_or_zero_operand (operands[1], TImode))" "#" @@ -2145,9 +2160,9 @@ (define_split (match_operand:TI 1 "register_operand" ""))] "reload_completed && ((TARGET_FPU - && ! TARGET_HARD_QUAD) - || (! fp_register_operand (operands[0], TImode) - && ! fp_register_operand (operands[1], TImode)))" + && !TARGET_HARD_QUAD) + || (!fp_register_operand (operands[0], TImode) + && !fp_register_operand (operands[1], TImode)))" [(clobber (const_int 0))] { rtx set_dest = operands[0]; @@ -2208,8 +2223,8 @@ (define_split (match_operand:TI 1 "memory_operand" ""))] "reload_completed && offsettable_memref_p (operands[1]) - && (! TARGET_HARD_QUAD - || ! fp_register_operand (operands[0], TImode))" + && (!TARGET_HARD_QUAD + || !fp_register_operand (operands[0], TImode))" [(clobber (const_int 0))] { rtx word0 = adjust_address (operands[1], DImode, 0); @@ -2242,8 +2257,8 @@ (define_split (match_operand:TI 1 "register_operand" ""))] "reload_completed && offsettable_memref_p (operands[0]) - && (! TARGET_HARD_QUAD - || ! fp_register_operand (operands[1], TImode))" + && (!TARGET_HARD_QUAD + || !fp_register_operand (operands[1], TImode))" [(clobber (const_int 0))] { rtx set_src = operands[1]; @@ -2360,9 +2375,11 @@ (define_expand "movdf" }) (define_insn "*movdf_insn_sp32" - [(set (match_operand:DF 0 "nonimmediate_operand" "=b,b,e,e,*r, f, e,T,W,U,T, f, *r, o,o") - (match_operand:DF 1 "input_operand" "G,C,e,e, f,*r,W#F,G,e,T,U,o#F,*roF,*rG,f"))] - "! TARGET_ARCH64 + [(set (match_operand:DF 0 "nonimmediate_operand" + "=b,b,e,e,*r, f, e,T,W,U,T, f, *r, o,o") + (match_operand:DF 1 "input_operand" + " G,C,e,e, f,*r,W#F,G,e,T,U,o#F,*roF,*rG,f"))] + "TARGET_ARCH32 && (register_operand (operands[0], DFmode) || register_or_zero_or_all_ones_operand (operands[1], DFmode))" "@ @@ -2417,7 +2434,7 @@ (define_split (match_operand:DF 1 "const_double_operand" ""))] "REG_P (operands[0]) && SPARC_INT_REG_P (REGNO (operands[0])) - && ! const_zero_operand (operands[1], GET_MODE (operands[0])) + && !const_zero_operand (operands[1], GET_MODE (operands[0])) && reload_completed" [(clobber (const_int 0))] { @@ -2443,8 +2460,8 @@ (define_split /* Slick... but this trick loses if this subreg constant part can be done in one insn. */ if (lo == hi - && ! SPARC_SETHI32_P (INTVAL (hi)) - && ! SPARC_SIMM13_P (INTVAL (hi))) + && !SPARC_SETHI32_P (INTVAL (hi)) + && !SPARC_SIMM13_P (INTVAL (hi))) { emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), gen_highpart (SImode, operands[0]))); @@ -2465,10 +2482,9 @@ (define_split (define_split [(set (match_operand:DF 0 "register_operand" "") (match_operand:DF 1 "register_operand" ""))] - "(! TARGET_V9 - || (! TARGET_ARCH64 - && sparc_split_regreg_legitimate (operands[0], - operands[1]))) + "(!TARGET_V9 + || (TARGET_ARCH32 + && sparc_split_regreg_legitimate (operands[0], operands[1]))) && reload_completed" [(clobber (const_int 0))] { @@ -2501,9 +2517,9 @@ (define_split [(set (match_operand:DF 0 "register_operand" "") (match_operand:DF 1 "memory_operand" ""))] "reload_completed - && ! TARGET_ARCH64 + && TARGET_ARCH32 && (((REGNO (operands[0]) % 2) != 0) - || ! mem_min_alignment (operands[1], 8)) + || !mem_min_alignment (operands[1], 8)) && offsettable_memref_p (operands[1])" [(clobber (const_int 0))] { @@ -2529,9 +2545,9 @@ (define_split [(set (match_operand:DF 0 "memory_operand" "") (match_operand:DF 1 "register_operand" ""))] "reload_completed - && ! TARGET_ARCH64 + && TARGET_ARCH32 && (((REGNO (operands[1]) % 2) != 0) - || ! mem_min_alignment (operands[0], 8)) + || !mem_min_alignment (operands[0], 8)) && offsettable_memref_p (operands[0])" [(clobber (const_int 0))] { @@ -2549,9 +2565,9 @@ (define_split [(set (match_operand:DF 0 "memory_operand" "") (match_operand:DF 1 "const_zero_operand" ""))] "reload_completed - && (! TARGET_V9 - || (! TARGET_ARCH64 - && ! mem_min_alignment (operands[0], 8))) + && (!TARGET_V9 + || (TARGET_ARCH32 + && !mem_min_alignment (operands[0], 8))) && offsettable_memref_p (operands[0])" [(clobber (const_int 0))] { @@ -2569,7 +2585,7 @@ (define_split [(set (match_operand:DF 0 "register_operand" "") (match_operand:DF 1 "const_zero_operand" ""))] "reload_completed - && ! TARGET_ARCH64 + && TARGET_ARCH32 && ((GET_CODE (operands[0]) == REG && SPARC_INT_REG_P (REGNO (operands[0]))) || (GET_CODE (operands[0]) == SUBREG @@ -2599,7 +2615,7 @@ (define_expand "movtf" (define_insn "*movtf_insn_sp32" [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o,U, r") (match_operand:TF 1 "input_operand" " G,oe,e,rGU,o,roG"))] - "! TARGET_ARCH64 + "TARGET_ARCH32 && (register_operand (operands[0], TFmode) || register_or_zero_operand (operands[1], TFmode))" "#" @@ -2610,7 +2626,7 @@ (define_insn "*movtf_insn_sp64" [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o, r") (match_operand:TF 1 "input_operand" "G,oe,e,rG,roG"))] "TARGET_ARCH64 - && ! TARGET_HARD_QUAD + && !TARGET_HARD_QUAD && (register_operand (operands[0], TFmode) || register_or_zero_operand (operands[1], TFmode))" "#" @@ -2639,11 +2655,11 @@ (define_split [(set (match_operand:TF 0 "register_operand" "") (match_operand:TF 1 "register_operand" ""))] "reload_completed - && (! TARGET_ARCH64 + && (TARGET_ARCH32 || (TARGET_FPU - && ! TARGET_HARD_QUAD) - || (! fp_register_operand (operands[0], TFmode) - && ! fp_register_operand (operands[1], TFmode)))" + && !TARGET_HARD_QUAD) + || (!fp_register_operand (operands[0], TFmode) + && !fp_register_operand (operands[1], TFmode)))" [(clobber (const_int 0))] { rtx set_dest = operands[0]; @@ -2704,9 +2720,9 @@ (define_split (match_operand:TF 1 "memory_operand" ""))] "(reload_completed && offsettable_memref_p (operands[1]) - && (! TARGET_ARCH64 - || ! TARGET_HARD_QUAD - || ! fp_register_operand (operands[0], TFmode)))" + && (TARGET_ARCH32 + || !TARGET_HARD_QUAD + || !fp_register_operand (operands[0], TFmode)))" [(clobber (const_int 0))] { rtx word0 = adjust_address (operands[1], DFmode, 0); @@ -2739,9 +2755,9 @@ (define_split (match_operand:TF 1 "register_operand" ""))] "(reload_completed && offsettable_memref_p (operands[0]) - && (! TARGET_ARCH64 - || ! TARGET_HARD_QUAD - || ! fp_register_operand (operands[1], TFmode)))" + && (TARGET_ARCH32 + || !TARGET_HARD_QUAD + || !fp_register_operand (operands[1], TFmode)))" [(clobber (const_int 0))] { rtx set_src = operands[1]; @@ -2772,7 +2788,7 @@ (define_expand "mov<I:mode>cc" (match_operand:I 3 "arith10_operand" "")))] "TARGET_V9 && !(<I:MODE>mode == DImode && TARGET_ARCH32)" { - if (! sparc_expand_conditional_move (<I:MODE>mode, operands)) + if (!sparc_expand_conditional_move (<I:MODE>mode, operands)) FAIL; DONE; }) @@ -2784,7 +2800,7 @@ (define_expand "mov<F:mode>cc" (match_operand:F 3 "register_operand" "")))] "TARGET_V9 && TARGET_FPU" { - if (! sparc_expand_conditional_move (<F:MODE>mode, operands)) + if (!sparc_expand_conditional_move (<F:MODE>mode, operands)) FAIL; DONE; }) @@ -2792,8 +2808,8 @@ (define_expand "mov<F:mode>cc" (define_insn "*mov<I:mode>_cc_v9" [(set (match_operand:I 0 "register_operand" "=r") (if_then_else:I (match_operator 1 "icc_or_fcc_comparison_operator" - [(match_operand 2 "icc_or_fcc_register_operand" "X") - (const_int 0)]) + [(match_operand 2 "icc_or_fcc_register_operand" "X") + (const_int 0)]) (match_operand:I 3 "arith11_operand" "rL") (match_operand:I 4 "register_operand" "0")))] "TARGET_V9 && !(<I:MODE>mode == DImode && TARGET_ARCH32)" @@ -2803,8 +2819,8 @@ (define_insn "*mov<I:mode>_cc_v9" (define_insn "*mov<I:mode>_cc_reg_sp64" [(set (match_operand:I 0 "register_operand" "=r") (if_then_else:I (match_operator 1 "v9_register_comparison_operator" - [(match_operand:DI 2 "register_operand" "r") - (const_int 0)]) + [(match_operand:DI 2 "register_operand" "r") + (const_int 0)]) (match_operand:I 3 "arith10_operand" "rM") (match_operand:I 4 "register_operand" "0")))] "TARGET_ARCH64" @@ -2814,8 +2830,8 @@ (define_insn "*mov<I:mode>_cc_reg_sp64" (define_insn "*movsf_cc_v9" [(set (match_operand:SF 0 "register_operand" "=f") (if_then_else:SF (match_operator 1 "icc_or_fcc_comparison_operator" - [(match_operand 2 "icc_or_fcc_register_operand" "X") - (const_int 0)]) + [(match_operand 2 "icc_or_fcc_register_operand" "X") + (const_int 0)]) (match_operand:SF 3 "register_operand" "f") (match_operand:SF 4 "register_operand" "0")))] "TARGET_V9 && TARGET_FPU" @@ -2825,8 +2841,8 @@ (define_insn "*movsf_cc_v9" (define_insn "*movsf_cc_reg_sp64" [(set (match_operand:SF 0 "register_operand" "=f") (if_then_else:SF (match_operator 1 "v9_register_comparison_operator" - [(match_operand:DI 2 "register_operand" "r") - (const_int 0)]) + [(match_operand:DI 2 "register_operand" "r") + (const_int 0)]) (match_operand:SF 3 "register_operand" "f") (match_operand:SF 4 "register_operand" "0")))] "TARGET_ARCH64 && TARGET_FPU" @@ -2837,8 +2853,8 @@ (define_insn "*movsf_cc_reg_sp64" (define_insn "movdf_cc_v9" [(set (match_operand:DF 0 "register_operand" "=e") (if_then_else:DF (match_operator 1 "icc_or_fcc_comparison_operator" - [(match_operand 2 "icc_or_fcc_register_operand" "X") - (const_int 0)]) + [(match_operand 2 "icc_or_fcc_register_operand" "X") + (const_int 0)]) (match_operand:DF 3 "register_operand" "e") (match_operand:DF 4 "register_operand" "0")))] "TARGET_V9 && TARGET_FPU" @@ -2850,8 +2866,8 @@ (define_insn "movdf_cc_v9" (define_insn "movdf_cc_reg_sp64" [(set (match_operand:DF 0 "register_operand" "=e") (if_then_else:DF (match_operator 1 "v9_register_comparison_operator" - [(match_operand:DI 2 "register_operand" "r") - (const_int 0)]) + [(match_operand:DI 2 "register_operand" "r") + (const_int 0)]) (match_operand:DF 3 "register_operand" "e") (match_operand:DF 4 "register_operand" "0")))] "TARGET_ARCH64 && TARGET_FPU" @@ -2862,8 +2878,8 @@ (define_insn "movdf_cc_reg_sp64" (define_insn "*movtf_cc_hq_v9" [(set (match_operand:TF 0 "register_operand" "=e") (if_then_else:TF (match_operator 1 "icc_or_fcc_comparison_operator" - [(match_operand 2 "icc_or_fcc_register_operand" "X") - (const_int 0)]) + [(match_operand 2 "icc_or_fcc_register_operand" "X") + (const_int 0)]) (match_operand:TF 3 "register_operand" "e") (match_operand:TF 4 "register_operand" "0")))] "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD" @@ -2873,8 +2889,8 @@ (define_insn "*movtf_cc_hq_v9" (define_insn "*movtf_cc_reg_hq_sp64" [(set (match_operand:TF 0 "register_operand" "=e") (if_then_else:TF (match_operator 1 "v9_register_comparison_operator" - [(match_operand:DI 2 "register_operand" "r") - (const_int 0)]) + [(match_operand:DI 2 "register_operand" "r") + (const_int 0)]) (match_operand:TF 3 "register_operand" "e") (match_operand:TF 4 "register_operand" "0")))] "TARGET_ARCH64 && TARGET_FPU && TARGET_HARD_QUAD" @@ -2884,8 +2900,8 @@ (define_insn "*movtf_cc_reg_hq_sp64" (define_insn_and_split "*movtf_cc_v9" [(set (match_operand:TF 0 "register_operand" "=e") (if_then_else:TF (match_operator 1 "icc_or_fcc_comparison_operator" - [(match_operand 2 "icc_or_fcc_register_operand" "X") - (const_int 0)]) + [(match_operand 2 "icc_or_fcc_register_operand" "X") + (const_int 0)]) (match_operand:TF 3 "register_operand" "e") (match_operand:TF 4 "register_operand" "0")))] "TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD" @@ -2905,13 +2921,17 @@ (define_insn_and_split "*movtf_cc_v9" if (reg_overlap_mentioned_p (dest1, srca2)) { - emit_insn (gen_movdf_cc_v9 (dest2, operands[1], operands[2], srca2, dest2)); - emit_insn (gen_movdf_cc_v9 (dest1, operands[1], operands[2], srca1, dest1)); + emit_insn (gen_movdf_cc_v9 (dest2, operands[1], operands[2], + srca2, dest2)); + emit_insn (gen_movdf_cc_v9 (dest1, operands[1], operands[2], + srca1, dest1)); } else { - emit_insn (gen_movdf_cc_v9 (dest1, operands[1], operands[2], srca1, dest1)); - emit_insn (gen_movdf_cc_v9 (dest2, operands[1], operands[2], srca2, dest2)); + emit_insn (gen_movdf_cc_v9 (dest1, operands[1], operands[2], + srca1, dest1)); + emit_insn (gen_movdf_cc_v9 (dest2, operands[1], operands[2], + srca2, dest2)); } DONE; } @@ -2920,11 +2940,11 @@ (define_insn_and_split "*movtf_cc_v9" (define_insn_and_split "*movtf_cc_reg_sp64" [(set (match_operand:TF 0 "register_operand" "=e") (if_then_else:TF (match_operator 1 "v9_register_comparison_operator" - [(match_operand:DI 2 "register_operand" "r") - (const_int 0)]) + [(match_operand:DI 2 "register_operand" "r") + (const_int 0)]) (match_operand:TF 3 "register_operand" "e") (match_operand:TF 4 "register_operand" "0")))] - "TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD" + "TARGET_ARCH64 && TARGET_FPU && !TARGET_HARD_QUAD" "#" "&& reload_completed" [(clobber (const_int 0))] @@ -2941,13 +2961,17 @@ (define_insn_and_split "*movtf_cc_reg_sp if (reg_overlap_mentioned_p (dest1, srca2)) { - emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2], srca2, dest2)); - emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2], srca1, dest1)); + emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2], + srca2, dest2)); + emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2], + srca1, dest1)); } else { - emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2], srca1, dest1)); - emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2], srca2, dest2)); + emit_insn (gen_movdf_cc_reg_sp64 (dest1, operands[1], operands[2], + srca1, dest1)); + emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2], + srca2, dest2)); } DONE; } @@ -3094,7 +3118,7 @@ (define_insn "*zero_extendsidi2_insn_sp6 (define_insn_and_split "*zero_extendsidi2_insn_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] - "! TARGET_ARCH64" + "TARGET_ARCH32" "#" "&& reload_completed" [(set (match_dup 2) (match_dup 1)) @@ -3450,8 +3474,7 @@ (define_insn "*cmp_zero_extract_sp64" (define_insn "extendsfdf2" [(set (match_operand:DF 0 "register_operand" "=e") - (float_extend:DF - (match_operand:SF 1 "register_operand" "f")))] + (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU" "fstod\t%1, %0" [(set_attr "type" "fp") @@ -3459,38 +3482,33 @@ (define_insn "extendsfdf2" (define_expand "extendsftf2" [(set (match_operand:TF 0 "nonimmediate_operand" "") - (float_extend:TF - (match_operand:SF 1 "register_operand" "")))] + (float_extend:TF (match_operand:SF 1 "register_operand" "")))] "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)" "emit_tfmode_cvt (FLOAT_EXTEND, operands); DONE;") (define_insn "*extendsftf2_hq" [(set (match_operand:TF 0 "register_operand" "=e") - (float_extend:TF - (match_operand:SF 1 "register_operand" "f")))] + (float_extend:TF (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU && TARGET_HARD_QUAD" "fstoq\t%1, %0" [(set_attr "type" "fp")]) (define_expand "extenddftf2" [(set (match_operand:TF 0 "nonimmediate_operand" "") - (float_extend:TF - (match_operand:DF 1 "register_operand" "")))] + (float_extend:TF (match_operand:DF 1 "register_operand" "")))] "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)" "emit_tfmode_cvt (FLOAT_EXTEND, operands); DONE;") (define_insn "*extenddftf2_hq" [(set (match_operand:TF 0 "register_operand" "=e") - (float_extend:TF - (match_operand:DF 1 "register_operand" "e")))] + (float_extend:TF (match_operand:DF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" "fdtoq\t%1, %0" [(set_attr "type" "fp")]) (define_insn "truncdfsf2" [(set (match_operand:SF 0 "register_operand" "=f") - (float_truncate:SF - (match_operand:DF 1 "register_operand" "e")))] + (float_truncate:SF (match_operand:DF 1 "register_operand" "e")))] "TARGET_FPU" "fdtos\t%1, %0" [(set_attr "type" "fp") @@ -3499,30 +3517,26 @@ (define_insn "truncdfsf2" (define_expand "trunctfsf2" [(set (match_operand:SF 0 "register_operand" "") - (float_truncate:SF - (match_operand:TF 1 "general_operand" "")))] + (float_truncate:SF (match_operand:TF 1 "general_operand" "")))] "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)" "emit_tfmode_cvt (FLOAT_TRUNCATE, operands); DONE;") (define_insn "*trunctfsf2_hq" [(set (match_operand:SF 0 "register_operand" "=f") - (float_truncate:SF - (match_operand:TF 1 "register_operand" "e")))] + (float_truncate:SF (match_operand:TF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" "fqtos\t%1, %0" [(set_attr "type" "fp")]) (define_expand "trunctfdf2" [(set (match_operand:DF 0 "register_operand" "") - (float_truncate:DF - (match_operand:TF 1 "general_operand" "")))] + (float_truncate:DF (match_operand:TF 1 "general_operand" "")))] "TARGET_FPU && (TARGET_HARD_QUAD || TARGET_ARCH64)" "emit_tfmode_cvt (FLOAT_TRUNCATE, operands); DONE;") (define_insn "*trunctfdf2_hq" [(set (match_operand:DF 0 "register_operand" "=e") - (float_truncate:DF - (match_operand:TF 1 "register_operand" "e")))] + (float_truncate:DF (match_operand:TF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" "fqtod\t%1, %0" [(set_attr "type" "fp")]) @@ -3562,7 +3576,7 @@ (define_insn "*floatsitf2_hq" (define_expand "floatunssitf2" [(set (match_operand:TF 0 "nonimmediate_operand" "") (unsigned_float:TF (match_operand:SI 1 "register_operand" "")))] - "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD" + "TARGET_FPU && TARGET_ARCH64 && !TARGET_HARD_QUAD" "emit_tfmode_cvt (UNSIGNED_FLOAT, operands); DONE;") ;; Now the same for 64 bit sources. @@ -3611,7 +3625,7 @@ (define_insn "*floatditf2_hq" (define_expand "floatunsditf2" [(set (match_operand:TF 0 "nonimmediate_operand" "") (unsigned_float:TF (match_operand:DI 1 "register_operand" "")))] - "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD" + "TARGET_FPU && TARGET_ARCH64 && !TARGET_HARD_QUAD" "emit_tfmode_cvt (UNSIGNED_FLOAT, operands); DONE;") ;; Convert a float to an actual integer. @@ -3650,7 +3664,7 @@ (define_insn "*fix_trunctfsi2_hq" (define_expand "fixuns_trunctfsi2" [(set (match_operand:SI 0 "register_operand" "") (unsigned_fix:SI (match_operand:TF 1 "general_operand" "")))] - "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD" + "TARGET_FPU && TARGET_ARCH64 && !TARGET_HARD_QUAD" "emit_tfmode_cvt (UNSIGNED_FIX, operands); DONE;") ;; Now the same, for V9 targets @@ -3699,7 +3713,7 @@ (define_insn "*fix_trunctfdi2_hq" (define_expand "fixuns_trunctfdi2" [(set (match_operand:DI 0 "register_operand" "") (unsigned_fix:DI (match_operand:TF 1 "general_operand" "")))] - "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD" + "TARGET_FPU && TARGET_ARCH64 && !TARGET_HARD_QUAD" "emit_tfmode_cvt (UNSIGNED_FIX, operands); DONE;") @@ -3711,7 +3725,7 @@ (define_expand "adddi3" (match_operand:DI 2 "arith_double_add_operand" "")))] "" { - if (!TARGET_ARCH64) + if (TARGET_ARCH32) { emit_insn (gen_adddi3_sp32 (operands[0], operands[1], operands[2])); DONE; @@ -3730,7 +3744,7 @@ (define_expand "uaddvdi4" (pc)))] "" { - if (!TARGET_64BIT) + if (TARGET_ARCH32) { emit_insn (gen_uaddvdi4_sp32 (operands[0], operands[1], operands[2])); rtx x = gen_rtx_LTU (VOIDmode, gen_rtx_REG (CCCmode, SPARC_ICC_REG), @@ -3753,7 +3767,7 @@ (define_expand "addvdi4" (pc)))] "" { - if (!TARGET_64BIT) + if (TARGET_ARCH32) { emit_insn (gen_addvdi4_sp32 (operands[0], operands[1], operands[2])); rtx x = gen_rtx_NE (VOIDmode, gen_rtx_REG (CCVmode, SPARC_ICC_REG), @@ -3768,7 +3782,7 @@ (define_insn_and_split "adddi3_sp32" (plus:DI (match_operand:DI 1 "register_operand" "%r") (match_operand:DI 2 "arith_double_operand" "rHI"))) (clobber (reg:CC CC_REG))] - "!TARGET_ARCH64" + "TARGET_ARCH32" "#" "&& reload_completed" [(parallel [(set (reg:CCC CC_REG) @@ -3796,7 +3810,7 @@ (define_insn_and_split "uaddvdi4_sp32" (match_dup 1))) (set (match_operand:DI 0 "register_operand" "=&r") (plus:DI (match_dup 1) (match_dup 2)))] - "!TARGET_ARCH64" + "TARGET_ARCH32" "#" "&& reload_completed" [(parallel [(set (reg:CCC CC_REG) @@ -3834,7 +3848,7 @@ (define_insn_and_split "addvdi4_sp32" (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_ADDV))) (set (match_operand:DI 0 "register_operand" "=&r") (plus:DI (match_dup 1) (match_dup 2)))] - "!TARGET_ARCH64" + "TARGET_ARCH32" "#" "&& reload_completed" [(parallel [(set (reg:CCC CC_REG) @@ -3869,7 +3883,7 @@ (define_insn_and_split "*addx_extend_sp3 (match_operand:SI 1 "register_operand" "%r") (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CCC CC_REG) (const_int 0)))))] - "! TARGET_ARCH64" + "TARGET_ARCH32" "#" "&& reload_completed" [(set (match_dup 3) (plus:SI (plus:SI (match_dup 1) (match_dup 2)) @@ -3884,7 +3898,7 @@ (define_insn_and_split "*adddi3_extend_s (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) (match_operand:DI 2 "register_operand" "r"))) (clobber (reg:CC CC_REG))] - "! TARGET_ARCH64" + "TARGET_ARCH32" "#" "&& reload_completed" [(parallel [(set (reg:CCC CC_REG) @@ -4104,7 +4118,7 @@ (define_expand "subdi3" (match_operand:DI 2 "arith_double_add_operand" "")))] "" { - if (!TARGET_ARCH64) + if (TARGET_ARCH32) { emit_insn (gen_subdi3_sp32 (operands[0], operands[1], operands[2])); DONE; @@ -4128,7 +4142,7 @@ (define_expand "usubvdi4" DONE; } - if (!TARGET_64BIT) + if (TARGET_ARCH32) { emit_insn (gen_usubvdi4_sp32 (operands[0], operands[1], operands[2])); rtx x = gen_rtx_LTU (VOIDmode, gen_rtx_REG (CCCmode, SPARC_ICC_REG), @@ -4151,7 +4165,7 @@ (define_expand "subvdi4" (pc)))] "" { - if (!TARGET_64BIT) + if (TARGET_ARCH32) { emit_insn (gen_subvdi4_sp32 (operands[0], operands[1], operands[2])); rtx x = gen_rtx_NE (VOIDmode, gen_rtx_REG (CCVmode, SPARC_ICC_REG), @@ -4166,7 +4180,7 @@ (define_insn_and_split "subdi3_sp32" (minus:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "arith_double_operand" "rHI"))) (clobber (reg:CC CC_REG))] - "! TARGET_ARCH64" + "TARGET_ARCH32" "#" "&& reload_completed" [(parallel [(set (reg:CC CC_REG) @@ -4192,7 +4206,7 @@ (define_insn_and_split "usubvdi4_sp32" (match_operand:DI 2 "arith_double_operand" "rHI"))) (set (match_operand:DI 0 "register_operand" "=&r") (minus:DI (match_dup 1) (match_dup 2)))] - "!TARGET_ARCH64" + "TARGET_ARCH32" "#" "&& reload_completed" [(parallel [(set (reg:CC CC_REG) @@ -4232,7 +4246,7 @@ (define_insn_and_split "subvdi4_sp32" (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_SUBV))) (set (match_operand:DI 0 "register_operand" "=&r") (minus:DI (match_dup 1) (match_dup 2)))] - "!TARGET_ARCH64" + "TARGET_ARCH32" "#" "&& reload_completed" [(parallel [(set (reg:CC CC_REG) @@ -4266,7 +4280,7 @@ (define_insn_and_split "*subx_extend_sp3 (match_operand:SI 1 "register_or_zero_operand" "rJ") (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CCC CC_REG) (const_int 0)))))] - "! TARGET_ARCH64" + "TARGET_ARCH32" "#" "&& reload_completed" [(set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 2)) @@ -4281,7 +4295,7 @@ (define_insn_and_split "*subdi3_extend_s (minus:DI (match_operand:DI 1 "register_operand" "r") (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))) (clobber (reg:CC CC_REG))] - "! TARGET_ARCH64" + "TARGET_ARCH32" "#" "&& reload_completed" [(parallel [(set (reg:CC CC_REG) @@ -4470,12 +4484,13 @@ (define_insn "*cmp_ccxv_minus_set" (define_insn "*cmp_ccv_minus_sltu_set" [(set (reg:CCV CC_REG) - (compare:CCV (minus:SI (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ") - (match_operand:SI 2 "arith_operand" "rI")) - (ltu:SI (reg:CC CC_REG) (const_int 0))) - (unspec:SI [(minus:SI (match_dup 1) (match_dup 2)) - (ltu:SI (reg:CC CC_REG) (const_int 0))] - UNSPEC_SUBV))) + (compare:CCV + (minus:SI (minus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ") + (match_operand:SI 2 "arith_operand" "rI")) + (ltu:SI (reg:CC CC_REG) (const_int 0))) + (unspec:SI [(minus:SI (match_dup 1) (match_dup 2)) + (ltu:SI (reg:CC CC_REG) (const_int 0))] + UNSPEC_SUBV))) (set (match_operand:SI 0 "register_operand" "=r") (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (ltu:SI (reg:CC CC_REG) (const_int 0))))] @@ -4526,7 +4541,9 @@ (define_insn "muldi3_v8plus" (clobber (match_scratch:SI 3 "=&h,X")) (clobber (match_scratch:SI 4 "=&h,X"))] "TARGET_V8PLUS" - "* return output_v8plus_mult (insn, operands, \"mulx\");" +{ + return output_v8plus_mult (insn, operands, \"mulx\"); +} [(set_attr "type" "multi") (set_attr "length" "9,8")]) @@ -4648,9 +4665,10 @@ (define_insn "const_mulsidi3_sp64" (define_expand "smulsi3_highpart" [(set (match_operand:SI 0 "register_operand" "") (truncate:SI - (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) - (sign_extend:DI (match_operand:SI 2 "arith_operand" ""))) - (const_int 32))))] + (lshiftrt:DI + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) + (sign_extend:DI (match_operand:SI 2 "arith_operand" ""))) + (const_int 32))))] "TARGET_HARD_MUL && TARGET_ARCH32" { if (CONSTANT_P (operands[2])) @@ -4677,9 +4695,10 @@ (define_expand "smulsi3_highpart" (define_insn "smulsi3_highpart_v8plus" [(set (match_operand:SI 0 "register_operand" "=h,r") (truncate:SI - (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) - (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r"))) - (match_operand:SI 3 "small_int_operand" "I,I")))) + (lshiftrt:DI + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r"))) + (match_operand:SI 3 "small_int_operand" "I,I")))) (clobber (match_scratch:SI 4 "=X,&h"))] "TARGET_V8PLUS" "@ @@ -4692,11 +4711,10 @@ (define_insn "smulsi3_highpart_v8plus" (define_insn "" [(set (match_operand:SI 0 "register_operand" "=h,r") (subreg:SI - (lshiftrt:DI - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) - (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r"))) - (match_operand:SI 3 "small_int_operand" "I,I")) - 4)) + (lshiftrt:DI + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "r,r"))) + (match_operand:SI 3 "small_int_operand" "I,I")) 4)) (clobber (match_scratch:SI 4 "=X,&h"))] "TARGET_V8PLUS" "@ @@ -4708,9 +4726,10 @@ (define_insn "" (define_insn "const_smulsi3_highpart_v8plus" [(set (match_operand:SI 0 "register_operand" "=h,r") (truncate:SI - (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) - (match_operand:DI 2 "small_int_operand" "I,I")) - (match_operand:SI 3 "small_int_operand" "I,I")))) + (lshiftrt:DI + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) + (match_operand:DI 2 "small_int_operand" "I,I")) + (match_operand:SI 3 "small_int_operand" "I,I")))) (clobber (match_scratch:SI 4 "=X,&h"))] "TARGET_V8PLUS" "@ @@ -4722,9 +4741,10 @@ (define_insn "const_smulsi3_highpart_v8p (define_insn "*smulsi3_highpart_sp32" [(set (match_operand:SI 0 "register_operand" "=r") (truncate:SI - (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) - (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))) - (const_int 32))))] + (lshiftrt:DI + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))) + (const_int 32))))] "TARGET_HARD_MUL32" "smul\t%1, %2, %%g0\n\trd\t%%y, %0" [(set_attr "type" "multi") @@ -4733,9 +4753,10 @@ (define_insn "*smulsi3_highpart_sp32" (define_insn "const_smulsi3_highpart" [(set (match_operand:SI 0 "register_operand" "=r") (truncate:SI - (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:DI 2 "small_int_operand" "i")) - (const_int 32))))] + (lshiftrt:DI + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) + (match_operand:DI 2 "small_int_operand" "i")) + (const_int 32))))] "TARGET_HARD_MUL32" "smul\t%1, %2, %%g0\n\trd\t%%y, %0" [(set_attr "type" "multi") @@ -4846,9 +4867,10 @@ (define_insn "const_umulsidi3_v8plus" (define_expand "umulsi3_highpart" [(set (match_operand:SI 0 "register_operand" "") (truncate:SI - (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) - (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))) - (const_int 32))))] + (lshiftrt:DI + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) + (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))) + (const_int 32))))] "TARGET_HARD_MUL && TARGET_ARCH32" { if (CONSTANT_P (operands[2])) @@ -4875,9 +4897,10 @@ (define_expand "umulsi3_highpart" (define_insn "umulsi3_highpart_v8plus" [(set (match_operand:SI 0 "register_operand" "=h,r") (truncate:SI - (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r")) - (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r"))) - (match_operand:SI 3 "small_int_operand" "I,I")))) + (lshiftrt:DI + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "r,r"))) + (match_operand:SI 3 "small_int_operand" "I,I")))) (clobber (match_scratch:SI 4 "=X,h"))] "TARGET_V8PLUS" "@ @@ -4889,9 +4912,10 @@ (define_insn "umulsi3_highpart_v8plus" (define_insn "const_umulsi3_highpart_v8plus" [(set (match_operand:SI 0 "register_operand" "=h,r") (truncate:SI - (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r")) - (match_operand:DI 2 "uns_small_int_operand" "")) - (match_operand:SI 3 "small_int_operand" "I,I")))) + (lshiftrt:DI + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r")) + (match_operand:DI 2 "uns_small_int_operand" "")) + (match_operand:SI 3 "small_int_operand" "I,I")))) (clobber (match_scratch:SI 4 "=X,h"))] "TARGET_V8PLUS" "@ @@ -4903,9 +4927,10 @@ (define_insn "const_umulsi3_highpart_v8p (define_insn "*umulsi3_highpart_sp32" [(set (match_operand:SI 0 "register_operand" "=r") (truncate:SI - (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) - (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))) - (const_int 32))))] + (lshiftrt:DI + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))) + (const_int 32))))] "TARGET_HARD_MUL32" "umul\t%1, %2, %%g0\n\trd\t%%y, %0" [(set_attr "type" "multi") @@ -4914,9 +4939,10 @@ (define_insn "*umulsi3_highpart_sp32" (define_insn "const_umulsi3_highpart" [(set (match_operand:SI 0 "register_operand" "=r") (truncate:SI - (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:DI 2 "uns_small_int_operand" "")) - (const_int 32))))] + (lshiftrt:DI + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) + (match_operand:DI 2 "uns_small_int_operand" "")) + (const_int 32))))] "TARGET_HARD_MUL32" "umul\t%1, %s2, %%g0\n\trd\t%%y, %0" [(set_attr "type" "multi") @@ -4925,16 +4951,14 @@ (define_insn "const_umulsi3_highpart" (define_expand "umulxhi_vis" [(set (match_operand:DI 0 "register_operand" "") - (truncate:DI - (lshiftrt:TI - (mult:TI (zero_extend:TI - (match_operand:DI 1 "arith_operand" "")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" ""))) - (const_int 64))))] + (truncate:DI + (lshiftrt:TI + (mult:TI (zero_extend:TI (match_operand:DI 1 "arith_operand" "")) + (zero_extend:TI (match_operand:DI 2 "arith_operand" ""))) + (const_int 64))))] "TARGET_VIS3" { - if (! TARGET_ARCH64) + if (TARGET_ARCH32) { emit_insn (gen_umulxhi_v8plus (operands[0], operands[1], operands[2])); DONE; @@ -4943,44 +4967,40 @@ (define_expand "umulxhi_vis" (define_insn "*umulxhi_sp64" [(set (match_operand:DI 0 "register_operand" "=r") - (truncate:DI - (lshiftrt:TI - (mult:TI (zero_extend:TI - (match_operand:DI 1 "arith_operand" "%r")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" "rI"))) - (const_int 64))))] + (truncate:DI + (lshiftrt:TI + (mult:TI (zero_extend:TI (match_operand:DI 1 "arith_operand" "%r")) + (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI"))) + (const_int 64))))] "TARGET_VIS3 && TARGET_ARCH64" "umulxhi\t%1, %2, %0" [(set_attr "type" "imul")]) (define_insn "umulxhi_v8plus" [(set (match_operand:DI 0 "register_operand" "=r,h") - (truncate:DI - (lshiftrt:TI - (mult:TI (zero_extend:TI - (match_operand:DI 1 "arith_operand" "%r,0")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" "rI,rI"))) - (const_int 64)))) + (truncate:DI + (lshiftrt:TI + (mult:TI (zero_extend:TI (match_operand:DI 1 "arith_operand" "%r,0")) + (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI,rI"))) + (const_int 64)))) (clobber (match_scratch:SI 3 "=&h,X")) (clobber (match_scratch:SI 4 "=&h,X"))] - "TARGET_VIS3 && ! TARGET_ARCH64" - "* return output_v8plus_mult (insn, operands, \"umulxhi\");" + "TARGET_VIS3 && TARGET_ARCH32" +{ + return output_v8plus_mult (insn, operands, \"umulxhi\"); +} [(set_attr "type" "imul") (set_attr "length" "9,8")]) (define_expand "xmulx_vis" [(set (match_operand:DI 0 "register_operand" "") - (truncate:DI - (unspec:TI [(zero_extend:TI - (match_operand:DI 1 "arith_operand" "")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" ""))] - UNSPEC_XMUL)))] + (truncate:DI + (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" "")) + (zero_extend:TI (match_operand:DI 2 "arith_operand" ""))] + UNSPEC_XMUL)))] "TARGET_VIS3" { - if (! TARGET_ARCH64) + if (TARGET_ARCH32) { emit_insn (gen_xmulx_v8plus (operands[0], operands[1], operands[2])); DONE; @@ -4989,44 +5009,40 @@ (define_expand "xmulx_vis" (define_insn "*xmulx_sp64" [(set (match_operand:DI 0 "register_operand" "=r") - (truncate:DI - (unspec:TI [(zero_extend:TI - (match_operand:DI 1 "arith_operand" "%r")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" "rI"))] - UNSPEC_XMUL)))] + (truncate:DI + (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" "%r")) + (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI"))] + UNSPEC_XMUL)))] "TARGET_VIS3 && TARGET_ARCH64" "xmulx\t%1, %2, %0" [(set_attr "type" "imul")]) (define_insn "xmulx_v8plus" [(set (match_operand:DI 0 "register_operand" "=r,h") - (truncate:DI - (unspec:TI [(zero_extend:TI - (match_operand:DI 1 "arith_operand" "%r,0")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" "rI,rI"))] - UNSPEC_XMUL))) + (truncate:DI + (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" "%r,0")) + (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI,rI"))] + UNSPEC_XMUL))) (clobber (match_scratch:SI 3 "=&h,X")) (clobber (match_scratch:SI 4 "=&h,X"))] - "TARGET_VIS3 && ! TARGET_ARCH64" - "* return output_v8plus_mult (insn, operands, \"xmulx\");" + "TARGET_VIS3 && TARGET_ARCH32" +{ + return output_v8plus_mult (insn, operands, \"xmulx\"); +} [(set_attr "type" "imul") (set_attr "length" "9,8")]) (define_expand "xmulxhi_vis" [(set (match_operand:DI 0 "register_operand" "") - (truncate:DI - (lshiftrt:TI - (unspec:TI [(zero_extend:TI - (match_operand:DI 1 "arith_operand" "")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" ""))] - UNSPEC_XMUL) - (const_int 64))))] + (truncate:DI + (lshiftrt:TI + (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" "")) + (zero_extend:TI (match_operand:DI 2 "arith_operand" ""))] + UNSPEC_XMUL) + (const_int 64))))] "TARGET_VIS3" { - if (! TARGET_ARCH64) + if (TARGET_ARCH32) { emit_insn (gen_xmulxhi_v8plus (operands[0], operands[1], operands[2])); DONE; @@ -5035,32 +5051,30 @@ (define_expand "xmulxhi_vis" (define_insn "*xmulxhi_sp64" [(set (match_operand:DI 0 "register_operand" "=r") - (truncate:DI - (lshiftrt:TI - (unspec:TI [(zero_extend:TI - (match_operand:DI 1 "arith_operand" "%r")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" "rI"))] - UNSPEC_XMUL) - (const_int 64))))] + (truncate:DI + (lshiftrt:TI + (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" "%r")) + (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI"))] + UNSPEC_XMUL) + (const_int 64))))] "TARGET_VIS3 && TARGET_ARCH64" "xmulxhi\t%1, %2, %0" [(set_attr "type" "imul")]) (define_insn "xmulxhi_v8plus" [(set (match_operand:DI 0 "register_operand" "=r,h") - (truncate:DI - (lshiftrt:TI - (unspec:TI [(zero_extend:TI - (match_operand:DI 1 "arith_operand" "%r,0")) - (zero_extend:TI - (match_operand:DI 2 "arith_operand" "rI,rI"))] - UNSPEC_XMUL) - (const_int 64)))) + (truncate:DI + (lshiftrt:TI + (unspec:TI [(zero_extend:TI (match_operand:DI 1 "arith_operand" "%r,0")) + (zero_extend:TI (match_operand:DI 2 "arith_operand" "rI,rI"))] + UNSPEC_XMUL) + (const_int 64)))) (clobber (match_scratch:SI 3 "=&h,X")) (clobber (match_scratch:SI 4 "=&h,X"))] - "TARGET_VIS3 && !TARGET_ARCH64" - "* return output_v8plus_mult (insn, operands, \"xmulxhi\");" + "TARGET_VIS3 && TARGET_ARCH32" +{ + return output_v8plus_mult (insn, operands, \"xmulxhi\"); +} [(set_attr "type" "imul") (set_attr "length" "9,8")]) @@ -5424,10 +5438,9 @@ (define_insn "*xor_not_si" (define_insn "*cmp_cc_arith_op" [(set (reg:CC CC_REG) - (compare:CC - (match_operator:SI 2 "cc_arith_operator" - [(match_operand:SI 0 "arith_operand" "%r") - (match_operand:SI 1 "arith_operand" "rI")]) + (compare:CC (match_operator:SI 2 "cc_arith_operator" + [(match_operand:SI 0 "arith_operand" "%r") + (match_operand:SI 1 "arith_operand" "rI")]) (const_int 0)))] "" "%A2cc\t%0, %1, %%g0" @@ -5435,10 +5448,9 @@ (define_insn "*cmp_cc_arith_op" (define_insn "*cmp_ccx_arith_op" [(set (reg:CCX CC_REG) - (compare:CCX - (match_operator:DI 2 "cc_arith_operator" - [(match_operand:DI 0 "arith_operand" "%r") - (match_operand:DI 1 "arith_operand" "rI")]) + (compare:CCX (match_operator:DI 2 "cc_arith_operator" + [(match_operand:DI 0 "arith_operand" "%r") + (match_operand:DI 1 "arith_operand" "rI")]) (const_int 0)))] "TARGET_ARCH64" "%A2cc\t%0, %1, %%g0" @@ -5446,26 +5458,26 @@ (define_insn "*cmp_ccx_arith_op" (define_insn "*cmp_cc_arith_op_set" [(set (reg:CC CC_REG) - (compare:CC - (match_operator:SI 3 "cc_arith_operator" - [(match_operand:SI 1 "arith_operand" "%r") - (match_operand:SI 2 "arith_operand" "rI")]) + (compare:CC (match_operator:SI 3 "cc_arith_operator" + [(match_operand:SI 1 "arith_operand" "%r") + (match_operand:SI 2 "arith_operand" "rI")]) (const_int 0))) (set (match_operand:SI 0 "register_operand" "=r") - (match_operator:SI 4 "cc_arith_operator" [(match_dup 1) (match_dup 2)]))] + (match_operator:SI 4 "cc_arith_operator" + [(match_dup 1) (match_dup 2)]))] "GET_CODE (operands[3]) == GET_CODE (operands[4])" "%A3cc\t%1, %2, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_arith_op_set" [(set (reg:CCX CC_REG) - (compare:CCX - (match_operator:DI 3 "cc_arith_operator" - [(match_operand:DI 1 "arith_operand" "%r") - (match_operand:DI 2 "arith_operand" "rI")]) + (compare:CCX (match_operator:DI 3 "cc_arith_operator" + [(match_operand:DI 1 "arith_operand" "%r") + (match_operand:DI 2 "arith_operand" "rI")]) (const_int 0))) (set (match_operand:DI 0 "register_operand" "=r") - (match_operator:DI 4 "cc_arith_operator" [(match_dup 1) (match_dup 2)]))] + (match_operator:DI 4 "cc_arith_operator" + [(match_dup 1) (match_dup 2)]))] "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])" "%A3cc\t%1, %2, %0" [(set_attr "type" "compare")]) @@ -5516,10 +5528,9 @@ (define_insn "*cmp_ccx_xor_not_set" (define_insn "*cmp_cc_arith_op_not" [(set (reg:CC CC_REG) - (compare:CC - (match_operator:SI 2 "cc_arith_not_operator" - [(not:SI (match_operand:SI 0 "arith_operand" "rI")) - (match_operand:SI 1 "register_or_zero_operand" "rJ")]) + (compare:CC (match_operator:SI 2 "cc_arith_not_operator" + [(not:SI (match_operand:SI 0 "arith_operand" "rI")) + (match_operand:SI 1 "register_or_zero_operand" "rJ")]) (const_int 0)))] "" "%B2cc\t%r1, %0, %%g0" @@ -5527,10 +5538,9 @@ (define_insn "*cmp_cc_arith_op_not" (define_insn "*cmp_ccx_arith_op_not" [(set (reg:CCX CC_REG) - (compare:CCX - (match_operator:DI 2 "cc_arith_not_operator" - [(not:DI (match_operand:DI 0 "arith_operand" "rI")) - (match_operand:DI 1 "register_or_zero_operand" "rJ")]) + (compare:CCX (match_operator:DI 2 "cc_arith_not_operator" + [(not:DI (match_operand:DI 0 "arith_operand" "rI")) + (match_operand:DI 1 "register_or_zero_operand" "rJ")]) (const_int 0)))] "TARGET_ARCH64" "%B2cc\t%r1, %0, %%g0" @@ -5538,28 +5548,26 @@ (define_insn "*cmp_ccx_arith_op_not" (define_insn "*cmp_cc_arith_op_not_set" [(set (reg:CC CC_REG) - (compare:CC - (match_operator:SI 3 "cc_arith_not_operator" - [(not:SI (match_operand:SI 1 "arith_operand" "rI")) - (match_operand:SI 2 "register_or_zero_operand" "rJ")]) + (compare:CC (match_operator:SI 3 "cc_arith_not_operator" + [(not:SI (match_operand:SI 1 "arith_operand" "rI")) + (match_operand:SI 2 "register_or_zero_operand" "rJ")]) (const_int 0))) (set (match_operand:SI 0 "register_operand" "=r") (match_operator:SI 4 "cc_arith_not_operator" - [(not:SI (match_dup 1)) (match_dup 2)]))] + [(not:SI (match_dup 1)) (match_dup 2)]))] "GET_CODE (operands[3]) == GET_CODE (operands[4])" "%B3cc\t%r2, %1, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_arith_op_not_set" [(set (reg:CCX CC_REG) - (compare:CCX - (match_operator:DI 3 "cc_arith_not_operator" - [(not:DI (match_operand:DI 1 "arith_operand" "rI")) - (match_operand:DI 2 "register_or_zero_operand" "rJ")]) + (compare:CCX (match_operator:DI 3 "cc_arith_not_operator" + [(not:DI (match_operand:DI 1 "arith_operand" "rI")) + (match_operand:DI 2 "register_or_zero_operand" "rJ")]) (const_int 0))) (set (match_operand:DI 0 "register_operand" "=r") (match_operator:DI 4 "cc_arith_not_operator" - [(not:DI (match_dup 1)) (match_dup 2)]))] + [(not:DI (match_dup 1)) (match_dup 2)]))] "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])" "%B3cc\t%r2, %1, %0" [(set_attr "type" "compare")]) @@ -5572,7 +5580,7 @@ (define_expand "negdi2" (neg:DI (match_operand:DI 1 "register_operand" "r")))] "" { - if (!TARGET_ARCH64) + if (TARGET_ARCH32) { emit_insn (gen_negdi2_sp32 (operands[0], operands[1])); DONE; @@ -5591,7 +5599,7 @@ (define_expand "unegvdi3" (pc)))] "" { - if (!TARGET_64BIT) + if (TARGET_ARCH32) { emit_insn (gen_unegvdi3_sp32 (operands[0], operands[1])); rtx x = gen_rtx_LTU (VOIDmode, gen_rtx_REG (CCCmode, SPARC_ICC_REG), @@ -5613,7 +5621,7 @@ (define_expand "negvdi3" (pc)))] "" { - if (!TARGET_64BIT) + if (TARGET_ARCH32) { emit_insn (gen_negvdi3_sp32 (operands[0], operands[1])); rtx x = gen_rtx_NE (VOIDmode, gen_rtx_REG (CCVmode, SPARC_ICC_REG), @@ -5627,7 +5635,7 @@ (define_insn_and_split "negdi2_sp32" [(set (match_operand:DI 0 "register_operand" "=&r") (neg:DI (match_operand:DI 1 "register_operand" "r"))) (clobber (reg:CC CC_REG))] - "! TARGET_ARCH64" + "TARGET_ARCH32" "#" "&& reload_completed" [(parallel [(set (reg:CCC CC_REG) @@ -5647,7 +5655,7 @@ (define_insn_and_split "unegvdi3_sp32" (const_int -1))) (set (match_operand:DI 0 "register_operand" "=&r") (neg:DI (match_dup 1)))] - "!TARGET_ARCH64" + "TARGET_ARCH32" "#" "&& reload_completed" [(parallel [(set (reg:CCC CC_REG) @@ -5676,7 +5684,7 @@ (define_insn_and_split "negvdi3_sp32" (unspec:DI [(match_dup 1)] UNSPEC_NEGV))) (set (match_operand:DI 0 "register_operand" "=&r") (neg:DI (match_dup 1)))] - "!TARGET_ARCH64" + "TARGET_ARCH32" "#" "&& reload_completed" [(parallel [(set (reg:CCC CC_REG) @@ -6435,7 +6443,7 @@ (define_expand "ashldi3" (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64 || TARGET_V8PLUS" { - if (! TARGET_ARCH64) + if (TARGET_ARCH32) { if (GET_CODE (operands[2]) == CONST_INT) FAIL; @@ -6462,7 +6470,9 @@ (define_insn "ashldi3_v8plus" (match_operand:SI 2 "arith_operand" "rI,rI,rI"))) (clobber (match_scratch:SI 3 "=X,X,&h"))] "TARGET_V8PLUS" - "* return output_v8plus_shift (insn ,operands, \"sllx\");" +{ + return output_v8plus_shift (insn ,operands, \"sllx\"); +} [(set_attr "type" "multi") (set_attr "length" "5,5,6")]) @@ -6491,11 +6501,11 @@ (define_insn "ashrsi3" (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "" - { - if (GET_CODE (operands[2]) == CONST_INT) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); - return "sra\t%1, %2, %0"; - } +{ + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + return "sra\t%1, %2, %0"; +} [(set_attr "type" "shift")]) (define_insn "*ashrsi3_extend" @@ -6526,7 +6536,7 @@ (define_expand "ashrdi3" (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64 || TARGET_V8PLUS" { - if (! TARGET_ARCH64) + if (TARGET_ARCH32) { if (GET_CODE (operands[2]) == CONST_INT) FAIL; /* prefer generic code in this case */ @@ -6540,12 +6550,11 @@ (define_insn "*ashrdi3_sp64" (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64" - - { - if (GET_CODE (operands[2]) == CONST_INT) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); - return "srax\t%1, %2, %0"; - } +{ + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); + return "srax\t%1, %2, %0"; +} [(set_attr "type" "shift")]) (define_insn "ashrdi3_v8plus" @@ -6554,7 +6563,9 @@ (define_insn "ashrdi3_v8plus" (match_operand:SI 2 "arith_operand" "rI,rI,rI"))) (clobber (match_scratch:SI 3 "=X,X,&h"))] "TARGET_V8PLUS" - "* return output_v8plus_shift (insn, operands, \"srax\");" +{ + return output_v8plus_shift (insn, operands, \"srax\"); +} [(set_attr "type" "multi") (set_attr "length" "5,5,6")]) @@ -6563,11 +6574,11 @@ (define_insn "lshrsi3" (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "" - { - if (GET_CODE (operands[2]) == CONST_INT) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); - return "srl\t%1, %2, %0"; - } +{ + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + return "srl\t%1, %2, %0"; +} [(set_attr "type" "shift")]) (define_insn "*lshrsi3_extend0" @@ -6576,11 +6587,11 @@ (define_insn "*lshrsi3_extend0" (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI"))))] "TARGET_ARCH64" - { - if (GET_CODE (operands[2]) == CONST_INT) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); - return "srl\t%1, %2, %0"; - } +{ + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + return "srl\t%1, %2, %0"; +} [(set_attr "type" "shift")]) ;; This handles the case where @@ -6616,7 +6627,7 @@ (define_expand "lshrdi3" (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64 || TARGET_V8PLUS" { - if (! TARGET_ARCH64) + if (TARGET_ARCH32) { if (GET_CODE (operands[2]) == CONST_INT) FAIL; @@ -6630,11 +6641,11 @@ (define_insn "*lshrdi3_sp64" (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64" - { - if (GET_CODE (operands[2]) == CONST_INT) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); - return "srlx\t%1, %2, %0"; - } +{ + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); + return "srlx\t%1, %2, %0"; +} [(set_attr "type" "shift")]) (define_insn "lshrdi3_v8plus" @@ -6643,7 +6654,9 @@ (define_insn "lshrdi3_v8plus" (match_operand:SI 2 "arith_operand" "rI,rI,rI"))) (clobber (match_scratch:SI 3 "=X,X,&h"))] "TARGET_V8PLUS" - "* return output_v8plus_shift (insn, operands, \"srlx\");" +{ + return output_v8plus_shift (insn, operands, \"srlx\"); +} [(set_attr "type" "multi") (set_attr "length" "5,5,6")]) @@ -6712,14 +6725,18 @@ (define_expand "jump" (define_insn "*jump_ubranch" [(set (pc) (label_ref (match_operand 0 "" "")))] - "! TARGET_CBCOND" - "* return output_ubranch (operands[0], insn);" + "!TARGET_CBCOND" +{ + return output_ubranch (operands[0], insn); +} [(set_attr "type" "uncond_branch")]) (define_insn "*jump_cbcond" [(set (pc) (label_ref (match_operand 0 "" "")))] "TARGET_CBCOND" - "* return output_ubranch (operands[0], insn);" +{ + return output_ubranch (operands[0], insn); +} [(set_attr "type" "uncond_cbcond")]) (define_expand "tablejump" @@ -6747,7 +6764,7 @@ (define_expand "tablejump" (define_insn "*tablejump_sp32" [(set (pc) (match_operand:SI 0 "address_operand" "p")) (use (label_ref (match_operand 1 "" "")))] - "! TARGET_ARCH64" + "TARGET_ARCH32" "jmp\t%a0%#" [(set_attr "type" "uncond_branch")]) @@ -6786,7 +6803,7 @@ (define_expand "call" Why cannot we have delay slots filled if it were a CALL? */ /* We accept negative sizes for untyped calls. */ - if (! TARGET_ARCH64 && INTVAL (operands[3]) != 0) + if (TARGET_ARCH32 && INTVAL (operands[3]) != 0) emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, @@ -6807,7 +6824,7 @@ (define_expand "call" fn_rtx = operands[0]; /* We accept negative sizes for untyped calls. */ - if (! TARGET_ARCH64 && INTVAL (operands[3]) != 0) + if (TARGET_ARCH32 && INTVAL (operands[3]) != 0) sparc_emit_call_insn (gen_rtx_PARALLEL (VOIDmode, @@ -6836,7 +6853,7 @@ (define_insn "*call_address_sp32" (match_operand 1 "" "")) (clobber (reg:SI O7_REG))] ;;- Do not use operand 1 for most machines. - "! TARGET_ARCH64" + "TARGET_ARCH32" "call\t%a0, %1%#" [(set_attr "type" "call")]) @@ -6845,7 +6862,7 @@ (define_insn "*call_symbolic_sp32" (match_operand 1 "" "")) (clobber (reg:SI O7_REG))] ;;- Do not use operand 1 for most machines. - "! TARGET_ARCH64" + "TARGET_ARCH32" "call\t%a0, %1%#" [(set_attr "type" "call")]) @@ -6875,7 +6892,7 @@ (define_insn "*call_address_struct_value (match_operand 2 "immediate_operand" "") (clobber (reg:SI O7_REG))] ;;- Do not use operand 1 for most machines. - "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0" + "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0" { operands[2] = GEN_INT (INTVAL (operands[2]) & 0xfff); return "call\t%a0, %1\n\t nop\n\tunimp\t%2"; @@ -6891,7 +6908,7 @@ (define_insn "*call_symbolic_struct_valu (match_operand 2 "immediate_operand" "") (clobber (reg:SI O7_REG))] ;;- Do not use operand 1 for most machines. - "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0" + "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0" { operands[2] = GEN_INT (INTVAL (operands[2]) & 0xfff); return "call\t%a0, %1\n\t nop\n\tunimp\t%2"; @@ -6907,7 +6924,7 @@ (define_insn "*call_address_untyped_stru (match_operand 2 "immediate_operand" "") (clobber (reg:SI O7_REG))] ;;- Do not use operand 1 for most machines. - "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0" + "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0" "call\t%a0, %1\n\t nop\n\tnop" [(set_attr "type" "call_no_delay_slot") (set_attr "length" "3")]) @@ -6920,7 +6937,7 @@ (define_insn "*call_symbolic_untyped_str (match_operand 2 "immediate_operand" "") (clobber (reg:SI O7_REG))] ;;- Do not use operand 1 for most machines. - "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0" + "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0" "call\t%a0, %1\n\t nop\n\tnop" [(set_attr "type" "call_no_delay_slot") (set_attr "length" "3")]) @@ -6958,7 +6975,7 @@ (define_insn "*call_value_address_sp32" (match_operand 2 "" ""))) (clobber (reg:SI O7_REG))] ;;- Do not use operand 2 for most machines. - "! TARGET_ARCH64" + "TARGET_ARCH32" "call\t%a1, %2%#" [(set_attr "type" "call")]) @@ -6968,7 +6985,7 @@ (define_insn "*call_value_symbolic_sp32" (match_operand 2 "" ""))) (clobber (reg:SI O7_REG))] ;;- Do not use operand 2 for most machines. - "! TARGET_ARCH64" + "TARGET_ARCH32" "call\t%a1, %2%#" [(set_attr "type" "call")]) @@ -7037,8 +7054,10 @@ (define_insn "*sibcall_symbolic_sp32" [(call (mem:SI (match_operand:SI 0 "symbolic_operand" "s")) (match_operand 1 "" "")) (return)] - "! TARGET_ARCH64" - "* return output_sibcall(insn, operands[0]);" + "TARGET_ARCH32" +{ + return output_sibcall(insn, operands[0]); +} [(set_attr "type" "sibcall")]) (define_insn "*sibcall_symbolic_sp64" @@ -7046,7 +7065,9 @@ (define_insn "*sibcall_symbolic_sp64" (match_operand 1 "" "")) (return)] "TARGET_ARCH64" - "* return output_sibcall(insn, operands[0]);" +{ + return output_sibcall(insn, operands[0]); +} [(set_attr "type" "sibcall")]) (define_expand "sibcall_value" @@ -7061,8 +7082,10 @@ (define_insn "*sibcall_value_symbolic_sp (call (mem:SI (match_operand:SI 1 "symbolic_operand" "s")) (match_operand 2 "" ""))) (return)] - "! TARGET_ARCH64" - "* return output_sibcall(insn, operands[1]);" + "TARGET_ARCH32" +{ + return output_sibcall(insn, operands[1]); +} [(set_attr "type" "sibcall")]) (define_insn "*sibcall_value_symbolic_sp64" @@ -7071,7 +7094,9 @@ (define_insn "*sibcall_value_symbolic_sp (match_operand 2 "" ""))) (return)] "TARGET_ARCH64" - "* return output_sibcall(insn, operands[1]);" +{ + return output_sibcall(insn, operands[1]); +} [(set_attr "type" "sibcall")]) @@ -7151,7 +7176,9 @@ (define_expand "return" (define_insn "*return_internal" [(return)] "" - "* return output_return (insn);" +{ + return output_return (insn); +} [(set_attr "type" "return") (set (attr "length") (cond [(eq_attr "calls_eh_return" "true") @@ -7215,7 +7242,9 @@ (define_insn "probe_stack_range<P:mode>" (match_operand:P 2 "register_operand" "r")] UNSPECV_PROBE_STACK_RANGE))] "" - "* return output_probe_stack_range (operands[0], operands[2]);" +{ + return output_probe_stack_range (operands[0], operands[2]); +} [(set_attr "type" "multi")]) ;; Prepare to return any type including a structure value. @@ -7228,7 +7257,7 @@ (define_expand "untyped_return" rtx valreg1 = gen_rtx_REG (DImode, 24); rtx result = operands[0]; - if (! TARGET_ARCH64) + if (TARGET_ARCH32) { rtx rtnreg = gen_rtx_REG (SImode, RETURN_ADDR_REGNUM); rtx value = gen_reg_rtx (SImode); @@ -7272,7 +7301,7 @@ (define_expand "untyped_return" (define_insn "update_return" [(unspec:SI [(match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "register_operand" "r")] UNSPEC_UPDATE_RETURN)] - "! TARGET_ARCH64" + "TARGET_ARCH32" { if (flag_delayed_branch) return "cmp\t%1, 0\n\tbe,a\t.+8\n\t add\t%0, 4, %0"; @@ -7297,7 +7326,7 @@ (define_expand "indirect_jump" (define_insn "*branch_sp32" [(set (pc) (match_operand:SI 0 "address_operand" "p"))] - "! TARGET_ARCH64" + "TARGET_ARCH32" "jmp\t%a0%#" [(set_attr "type" "uncond_branch")]) @@ -7376,7 +7405,9 @@ (define_expand "builtin_setjmp_receiver" (define_insn "flush_register_windows" [(unspec_volatile [(const_int 0)] UNSPECV_FLUSHW)] "" - { return TARGET_V9 ? "flushw" : "ta\t3"; } +{ + return TARGET_V9 ? "flushw" : "ta\t3"; +} [(set_attr "type" "flushw")]) ;; Special pattern for the FLUSH instruction. @@ -7384,7 +7415,9 @@ (define_insn "flush_register_windows" (define_insn "flush<P:mode>" [(unspec_volatile [(match_operand:P 0 "memory_operand" "m")] UNSPECV_FLUSH)] "" - { return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; } +{ + return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; +} [(set_attr "type" "iflush")]) ;; Special insns to load and store the 32-bit FP Status Register. @@ -7405,29 +7438,12 @@ (define_insn "stfsr" ;; Find first set instructions. -;; The scan instruction searches from the most significant bit while ffs -;; searches from the least significant bit. The bit index and treatment of -;; zero also differ. It takes at least 7 instructions to get the proper -;; result. Here is an obvious 8 instruction sequence. - -;; XXX -(define_insn "ffssi2" - [(set (match_operand:SI 0 "register_operand" "=&r") - (ffs:SI (match_operand:SI 1 "register_operand" "r"))) - (clobber (match_scratch:SI 2 "=&r"))] - "TARGET_SPARCLITE || TARGET_SPARCLET" -{ - return "sub\t%%g0, %1, %0\;and\t%0, %1, %0\;scan\t%0, 0, %0\;mov\t32, %2\;sub\t%2, %0, %0\;sra\t%0, 31, %2\;and\t%2, 31, %2\;add\t%2, %0, %0"; -} - [(set_attr "type" "multi") - (set_attr "length" "8")]) - (define_expand "popcountdi2" [(set (match_operand:DI 0 "register_operand" "") (popcount:DI (match_operand:DI 1 "register_operand" "")))] "TARGET_POPC" { - if (! TARGET_ARCH64) + if (TARGET_ARCH32) { emit_insn (gen_popcountdi_v8plus (operands[0], operands[1])); DONE; @@ -7444,7 +7460,7 @@ (define_insn "popcountdi_v8plus" [(set (match_operand:DI 0 "register_operand" "=r") (popcount:DI (match_operand:DI 1 "register_operand" "r"))) (clobber (match_scratch:SI 2 "=&h"))] - "TARGET_POPC && ! TARGET_ARCH64" + "TARGET_POPC && TARGET_ARCH32" { if (sparc_check_64 (operands[1], insn) <= 0) output_asm_insn ("srl\t%L1, 0, %L1", operands); @@ -7460,7 +7476,7 @@ (define_expand "popcountsi2" (truncate:SI (popcount:DI (match_dup 2))))] "TARGET_POPC" { - if (! TARGET_ARCH64) + if (TARGET_ARCH32) { emit_insn (gen_popcountsi_v8plus (operands[0], operands[1])); DONE; @@ -7479,7 +7495,7 @@ (define_insn "*popcountsi_sp64" (define_insn "popcountsi_v8plus" [(set (match_operand:SI 0 "register_operand" "=r") (popcount:SI (match_operand:SI 1 "register_operand" "r")))] - "TARGET_POPC && ! TARGET_ARCH64" + "TARGET_POPC && TARGET_ARCH32" { if (sparc_check_64 (operands[1], insn) <= 0) output_asm_insn ("srl\t%1, 0, %1", operands); @@ -7493,7 +7509,7 @@ (define_expand "clzdi2" (clz:DI (match_operand:DI 1 "register_operand" "")))] "TARGET_VIS3" { - if (! TARGET_ARCH64) + if (TARGET_ARCH32) { emit_insn (gen_clzdi_v8plus (operands[0], operands[1])); DONE; @@ -7511,7 +7527,7 @@ (define_insn "clzdi_v8plus" [(set (match_operand:DI 0 "register_operand" "=r") (clz:DI (match_operand:DI 1 "register_operand" "r"))) (clobber (match_scratch:SI 2 "=&h"))] - "TARGET_VIS3 && ! TARGET_ARCH64" + "TARGET_VIS3 && TARGET_ARCH32" { if (sparc_check_64 (operands[1], insn) <= 0) output_asm_insn ("srl\t%L1, 0, %L1", operands); @@ -7529,7 +7545,7 @@ (define_expand "clzsi2" (minus:SI (match_dup 3) (const_int 32)))] "TARGET_VIS3" { - if (! TARGET_ARCH64) + if (TARGET_ARCH32) { emit_insn (gen_clzsi_v8plus (operands[0], operands[1])); DONE; @@ -7552,7 +7568,7 @@ (define_insn "*clzsi_sp64" (define_insn "clzsi_v8plus" [(set (match_operand:SI 0 "register_operand" "=r") (clz:SI (match_operand:SI 1 "register_operand" "r")))] - "TARGET_VIS3 && ! TARGET_ARCH64" + "TARGET_VIS3 && TARGET_ARCH32" { if (sparc_check_64 (operands[1], insn) <= 0) output_asm_insn ("srl\t%1, 0, %1", operands); @@ -7708,8 +7724,8 @@ (define_peephole2 (const_int 0)))] "(rtx_equal_p (operands[2], operands[0]) || rtx_equal_p (operands[2], operands[1])) - && ! SPARC_FP_REG_P (REGNO (operands[0])) - && ! SPARC_FP_REG_P (REGNO (operands[1]))" + && !SPARC_FP_REG_P (REGNO (operands[0])) + && !SPARC_FP_REG_P (REGNO (operands[1]))" [(parallel [(set (match_dup 0) (match_dup 1)) (set (reg:CC CC_REG) (compare:CC (match_dup 1) (const_int 0)))])] @@ -7724,8 +7740,8 @@ (define_peephole2 "TARGET_ARCH64 && (rtx_equal_p (operands[2], operands[0]) || rtx_equal_p (operands[2], operands[1])) - && ! SPARC_FP_REG_P (REGNO (operands[0])) - && ! SPARC_FP_REG_P (REGNO (operands[1]))" + && !SPARC_FP_REG_P (REGNO (operands[0])) + && !SPARC_FP_REG_P (REGNO (operands[1]))" [(parallel [(set (match_dup 0) (match_dup 1)) (set (reg:CCX CC_REG) (compare:CCX (match_dup 1) (const_int 0)))])] @@ -7734,10 +7750,10 @@ (define_peephole2 ;; Prefetch instructions. -;; ??? UltraSPARC-III note: A memory operation loading into the floating point register -;; ??? file, if it hits the prefetch cache, has a chance to dual-issue with other memory -;; ??? operations. With DFA we might be able to model this, but it requires a lot of -;; ??? state. +;; ??? UltraSPARC-III note: A memory operation loading into the floating point +;; register file, if it hits the prefetch cache, has a chance to dual-issue +;; with other memory operations. With DFA we might be able to model this, +;; but it requires a lot of state. (define_expand "prefetch" [(match_operand 0 "address_operand" "") (match_operand 1 "const_int_operand" "") @@ -7814,7 +7830,7 @@ (define_expand "ctrapsi4" [(trap_if (match_operator 0 "comparison_operator" [(match_operand:SI 1 "compare_operand" "") (match_operand:SI 2 "arith_operand" "")]) - (match_operand 3 "arith_operand"))] + (match_operand 3 "arith_operand"))] "" { operands[1] = gen_compare_reg (operands[0]); @@ -7827,7 +7843,7 @@ (define_expand "ctrapdi4" [(trap_if (match_operator 0 "comparison_operator" [(match_operand:DI 1 "compare_operand" "") (match_operand:DI 2 "arith_operand" "")]) - (match_operand 3 "arith_operand"))] + (match_operand 3 "arith_operand"))] "TARGET_ARCH64" { operands[1] = gen_compare_reg (operands[0]); @@ -7838,7 +7854,7 @@ (define_expand "ctrapdi4" (define_insn "*trapsi_insn" [(trap_if (match_operator 0 "icc_comparison_operator" - [(reg:CC CC_REG) (const_int 0)]) + [(reg:CC CC_REG) (const_int 0)]) (match_operand:SI 1 "arith_operand" "rM"))] "" { @@ -7851,7 +7867,7 @@ (define_insn "*trapsi_insn" (define_insn "*trapdi_insn" [(trap_if (match_operator 0 "icc_comparison_operator" - [(reg:CCX CC_REG) (const_int 0)]) + [(reg:CCX CC_REG) (const_int 0)]) (match_operand:SI 1 "arith_operand" "rM"))] "TARGET_V9" "t%C0\t%%xcc, %1" @@ -8094,10 +8110,11 @@ (define_insn "*tldo_ldub_sp32" (define_insn "*tldo_ldub1_sp32" [(set (match_operand:HI 0 "register_operand" "=r") - (zero_extend:HI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:SI 1 "register_operand" "r")))))] + (zero_extend:HI + (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:SI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH32" "ldub\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "load") @@ -8105,10 +8122,11 @@ (define_insn "*tldo_ldub1_sp32" (define_insn "*tldo_ldub2_sp32" [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extend:SI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:SI 1 "register_operand" "r")))))] + (zero_extend:SI + (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:SI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH32" "ldub\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "load") @@ -8116,10 +8134,11 @@ (define_insn "*tldo_ldub2_sp32" (define_insn "*tldo_ldsb1_sp32" [(set (match_operand:HI 0 "register_operand" "=r") - (sign_extend:HI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:SI 1 "register_operand" "r")))))] + (sign_extend:HI + (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:SI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH32" "ldsb\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "sload") @@ -8127,10 +8146,11 @@ (define_insn "*tldo_ldsb1_sp32" (define_insn "*tldo_ldsb2_sp32" [(set (match_operand:SI 0 "register_operand" "=r") - (sign_extend:SI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:SI 1 "register_operand" "r")))))] + (sign_extend:SI + (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:SI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH32" "ldsb\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "sload") @@ -8149,10 +8169,11 @@ (define_insn "*tldo_ldub_sp64" (define_insn "*tldo_ldub1_sp64" [(set (match_operand:HI 0 "register_operand" "=r") - (zero_extend:HI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:DI 1 "register_operand" "r")))))] + (zero_extend:HI + (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:DI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH64" "ldub\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "load") @@ -8160,10 +8181,11 @@ (define_insn "*tldo_ldub1_sp64" (define_insn "*tldo_ldub2_sp64" [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extend:SI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:DI 1 "register_operand" "r")))))] + (zero_extend:SI + (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:DI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH64" "ldub\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "load") @@ -8171,10 +8193,11 @@ (define_insn "*tldo_ldub2_sp64" (define_insn "*tldo_ldub3_sp64" [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:DI 1 "register_operand" "r")))))] + (zero_extend:DI + (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:DI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH64" "ldub\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "load") @@ -8182,10 +8205,11 @@ (define_insn "*tldo_ldub3_sp64" (define_insn "*tldo_ldsb1_sp64" [(set (match_operand:HI 0 "register_operand" "=r") - (sign_extend:HI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:DI 1 "register_operand" "r")))))] + (sign_extend:HI + (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:DI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH64" "ldsb\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "sload") @@ -8193,10 +8217,11 @@ (define_insn "*tldo_ldsb1_sp64" (define_insn "*tldo_ldsb2_sp64" [(set (match_operand:SI 0 "register_operand" "=r") - (sign_extend:SI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:DI 1 "register_operand" "r")))))] + (sign_extend:SI + (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:DI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH64" "ldsb\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "sload") @@ -8204,10 +8229,11 @@ (define_insn "*tldo_ldsb2_sp64" (define_insn "*tldo_ldsb3_sp64" [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:DI 1 "register_operand" "r")))))] + (sign_extend:DI + (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:DI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH64" "ldsb\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "sload") @@ -8226,10 +8252,11 @@ (define_insn "*tldo_lduh_sp32" (define_insn "*tldo_lduh1_sp32" [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extend:SI (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:SI 1 "register_operand" "r")))))] + (zero_extend:SI + (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:SI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH32" "lduh\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "load") @@ -8237,10 +8264,11 @@ (define_insn "*tldo_lduh1_sp32" (define_insn "*tldo_ldsh1_sp32" [(set (match_operand:SI 0 "register_operand" "=r") - (sign_extend:SI (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:SI 1 "register_operand" "r")))))] + (sign_extend:SI + (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:SI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH32" "ldsh\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "sload") @@ -8259,10 +8287,11 @@ (define_insn "*tldo_lduh_sp64" (define_insn "*tldo_lduh1_sp64" [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extend:SI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:DI 1 "register_operand" "r")))))] + (zero_extend:SI + (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:DI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH64" "lduh\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "load") @@ -8270,10 +8299,11 @@ (define_insn "*tldo_lduh1_sp64" (define_insn "*tldo_lduh2_sp64" [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:DI 1 "register_operand" "r")))))] + (zero_extend:DI + (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:DI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH64" "lduh\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "load") @@ -8281,10 +8311,11 @@ (define_insn "*tldo_lduh2_sp64" (define_insn "*tldo_ldsh1_sp64" [(set (match_operand:SI 0 "register_operand" "=r") - (sign_extend:SI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:DI 1 "register_operand" "r")))))] + (sign_extend:SI + (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:DI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH64" "ldsh\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "sload") @@ -8292,10 +8323,11 @@ (define_insn "*tldo_ldsh1_sp64" (define_insn "*tldo_ldsh2_sp64" [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:DI 1 "register_operand" "r")))))] + (sign_extend:DI + (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:DI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH64" "ldsh\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "sload") @@ -8323,20 +8355,22 @@ (define_insn "*tldo_lduw_sp64" (define_insn "*tldo_lduw1_sp64" [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:DI 1 "register_operand" "r")))))] + (zero_extend:DI + (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:DI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH64" "lduw\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "load")]) (define_insn "*tldo_ldsw1_sp64" [(set (match_operand:DI 0 "register_operand" "=r") - (sign_extend:DI (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") - (match_operand 3 "tld_symbolic_operand" "")] - UNSPEC_TLSLDO) - (match_operand:DI 1 "register_operand" "r")))))] + (sign_extend:DI + (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r") + (match_operand 3 "tld_symbolic_operand" "")] + UNSPEC_TLSLDO) + (match_operand:DI 1 "register_operand" "r")))))] "TARGET_TLS && TARGET_ARCH64" "ldsw\t[%1 + %2], %0, %%tldo_add(%3)" [(set_attr "type" "sload") @@ -8585,7 +8619,7 @@ (define_insn "*mov<VM64:mode>_insn_sp32" [(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,*r, f,e,m,m,U,T, o,*r") (match_operand:VM64 1 "input_operand" "Y,C,e, f,*r,m,e,Y,T,U,*r,*r"))] "TARGET_VIS - && ! TARGET_ARCH64 + && TARGET_ARCH32 && (register_operand (operands[0], <VM64:MODE>mode) || register_or_zero_or_all_ones_operand (operands[1], <VM64:MODE>mode))" "@ @@ -8611,9 +8645,9 @@ (define_split (match_operand:VM64 1 "register_operand" ""))] "reload_completed && TARGET_VIS - && ! TARGET_ARCH64 + && TARGET_ARCH32 && (((REGNO (operands[1]) % 2) != 0) - || ! mem_min_alignment (operands[0], 8)) + || !mem_min_alignment (operands[0], 8)) && offsettable_memref_p (operands[0])" [(clobber (const_int 0))] { @@ -8632,7 +8666,7 @@ (define_split (match_operand:VM64 1 "register_operand" ""))] "reload_completed && TARGET_VIS - && ! TARGET_ARCH64 + && TARGET_ARCH32 && sparc_split_regreg_legitimate (operands[0], operands[1])" [(clobber (const_int 0))] { @@ -8661,7 +8695,7 @@ (define_split DONE; }) -(define_expand "vec_init<mode>" +(define_expand "vec_init<VMALL:mode>" [(match_operand:VMALL 0 "register_operand" "") (match_operand:VMALL 1 "" "")] "TARGET_VIS" @@ -8675,7 +8709,7 @@ (define_code_attr plusminus_insn [(plus (define_mode_iterator VADDSUB [V1SI V2SI V2HI V4HI]) -(define_insn "<plusminus_insn><mode>3" +(define_insn "<plusminus_insn><VADDSUB:mode>3" [(set (match_operand:VADDSUB 0 "register_operand" "=<vconstr>") (plusminus:VADDSUB (match_operand:VADDSUB 1 "register_operand" "<vconstr>") (match_operand:VADDSUB 2 "register_operand" "<vconstr>")))] @@ -8692,7 +8726,7 @@ (define_code_iterator vlop [ior and xor] (define_code_attr vlinsn [(ior "or") (and "and") (xor "xor")]) (define_code_attr vlninsn [(ior "nor") (and "nand") (xor "xnor")]) -(define_insn "<code><mode>3" +(define_insn "*<vlop:code><VL:mode>3" [(set (match_operand:VL 0 "register_operand" "=<vconstr>") (vlop:VL (match_operand:VL 1 "register_operand" "<vconstr>") (match_operand:VL 2 "register_operand" "<vconstr>")))] @@ -8702,7 +8736,7 @@ (define_insn "<code><mode>3" (set_attr "fptype" "<vfptype>") (set_attr "v3pipe" "true")]) -(define_insn "*not_<code><mode>3" +(define_insn "*not_<vlop:code><VL:mode>3" [(set (match_operand:VL 0 "register_operand" "=<vconstr>") (not:VL (vlop:VL (match_operand:VL 1 "register_operand" "<vconstr>") (match_operand:VL 2 "register_operand" "<vconstr>"))))] @@ -8713,7 +8747,7 @@ (define_insn "*not_<code><mode>3" (set_attr "v3pipe" "true")]) ;; (ior (not (op1)) (not (op2))) is the canonical form of NAND. -(define_insn "*nand<mode>_vis" +(define_insn "*nand<VL:mode>_vis" [(set (match_operand:VL 0 "register_operand" "=<vconstr>") (ior:VL (not:VL (match_operand:VL 1 "register_operand" "<vconstr>")) (not:VL (match_operand:VL 2 "register_operand" "<vconstr>"))))] @@ -8725,7 +8759,7 @@ (define_insn "*nand<mode>_vis" (define_code_iterator vlnotop [ior and]) -(define_insn "*<code>_not1<mode>_vis" +(define_insn "*<vlnotop:code>_not1<VL:mode>_vis" [(set (match_operand:VL 0 "register_operand" "=<vconstr>") (vlnotop:VL (not:VL (match_operand:VL 1 "register_operand" "<vconstr>")) (match_operand:VL 2 "register_operand" "<vconstr>")))] @@ -8735,7 +8769,7 @@ (define_insn "*<code>_not1<mode>_vis" (set_attr "fptype" "<vfptype>") (set_attr "v3pipe" "true")]) -(define_insn "*<code>_not2<mode>_vis" +(define_insn "*<vlnotop:code>_not2<VL:mode>_vis" [(set (match_operand:VL 0 "register_operand" "=<vconstr>") (vlnotop:VL (match_operand:VL 1 "register_operand" "<vconstr>") (not:VL (match_operand:VL 2 "register_operand" "<vconstr>"))))] @@ -8745,7 +8779,7 @@ (define_insn "*<code>_not2<mode>_vis" (set_attr "fptype" "<vfptype>") (set_attr "v3pipe" "true")]) -(define_insn "one_cmpl<mode>2" +(define_insn "one_cmpl<VL:mode>2" [(set (match_operand:VL 0 "register_operand" "=<vconstr>") (not:VL (match_operand:VL 1 "register_operand" "<vconstr>")))] "TARGET_VIS" @@ -8913,7 +8947,7 @@ (define_expand "wrgsr_vis" [(set (reg:DI GSR_REG) (match_operand:DI 0 "arith_operand" ""))] "TARGET_VIS" { - if (! TARGET_ARCH64) + if (TARGET_ARCH32) { emit_insn (gen_wrgsr_v8plus (operands[0])); DONE; @@ -8929,7 +8963,7 @@ (define_insn "*wrgsr_sp64" (define_insn "wrgsr_v8plus" [(set (reg:DI GSR_REG) (match_operand:DI 0 "arith_operand" "I,r")) (clobber (match_scratch:SI 1 "=X,&h"))] - "TARGET_VIS && ! TARGET_ARCH64" + "TARGET_VIS && TARGET_ARCH32" { if (GET_CODE (operands[0]) == CONST_INT || sparc_check_64 (operands[0], insn)) @@ -8944,7 +8978,7 @@ (define_expand "rdgsr_vis" [(set (match_operand:DI 0 "register_operand" "") (reg:DI GSR_REG))] "TARGET_VIS" { - if (! TARGET_ARCH64) + if (TARGET_ARCH32) { emit_insn (gen_rdgsr_v8plus (operands[0])); DONE; @@ -8960,7 +8994,7 @@ (define_insn "*rdgsr_sp64" (define_insn "rdgsr_v8plus" [(set (match_operand:DI 0 "register_operand" "=r") (reg:DI GSR_REG)) (clobber (match_scratch:SI 1 "=&h"))] - "TARGET_VIS && ! TARGET_ARCH64" + "TARGET_VIS && TARGET_ARCH32" { return "rd\t%%gsr, %1\n\tsrlx\t%1, 32, %H0\n\tmov %1, %L0"; } @@ -9110,28 +9144,28 @@ (define_code_iterator gcond [le ne gt eq (define_mode_iterator GCM [V4HI V2SI]) (define_mode_attr gcm_name [(V4HI "16") (V2SI "32")]) -(define_insn "fcmp<code><GCM:gcm_name><P:mode>_vis" +(define_insn "fcmp<gcond:code><GCM:gcm_name><P:mode>_vis" [(set (match_operand:P 0 "register_operand" "=r") (unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e") (match_operand:GCM 2 "register_operand" "e"))] UNSPEC_FCMP))] "TARGET_VIS" - "fcmp<code><GCM:gcm_name>\t%1, %2, %0" + "fcmp<gcond:code><GCM:gcm_name>\t%1, %2, %0" [(set_attr "type" "visl") (set_attr "fptype" "double") (set_attr "v3pipe" "true")]) -(define_insn "fpcmp<code>8<P:mode>_vis" +(define_insn "fpcmp<gcond:code>8<P:mode>_vis" [(set (match_operand:P 0 "register_operand" "=r") (unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e") (match_operand:V8QI 2 "register_operand" "e"))] UNSPEC_FCMP))] "TARGET_VIS4" - "fpcmp<code>8\t%1, %2, %0" + "fpcmp<gcond:code>8\t%1, %2, %0" [(set_attr "type" "visl") (set_attr "fptype" "double")]) -(define_expand "vcond<mode><mode>" +(define_expand "vcond<GCM:mode><GCM:mode>" [(match_operand:GCM 0 "register_operand" "") (match_operand:GCM 1 "register_operand" "") (match_operand:GCM 2 "register_operand" "") @@ -9140,9 +9174,7 @@ (define_expand "vcond<mode><mode>" (match_operand:GCM 5 "register_operand" "")])] "TARGET_VIS3" { - sparc_expand_vcond (<MODE>mode, operands, - UNSPEC_CMASK<gcm_name>, - UNSPEC_FCMP); + sparc_expand_vcond (<MODE>mode, operands, UNSPEC_CMASK<gcm_name>, UNSPEC_FCMP); DONE; }) @@ -9155,9 +9187,7 @@ (define_expand "vconduv8qiv8qi" (match_operand:V8QI 5 "register_operand" "")])] "TARGET_VIS3" { - sparc_expand_vcond (V8QImode, operands, - UNSPEC_CMASK8, - UNSPEC_FUCMP); + sparc_expand_vcond (V8QImode, operands, UNSPEC_CMASK8, UNSPEC_FUCMP); DONE; }) @@ -9247,7 +9277,7 @@ (define_expand "vec_perm_constv8qi" ;; Unlike constant permutation, we can vastly simplify the compression of ;; the 64-bit selector input to the 32-bit %gsr value by knowing what the ;; width of the input is. -(define_expand "vec_perm<mode>" +(define_expand "vec_perm<VM64:mode>" [(match_operand:VM64 0 "register_operand" "") (match_operand:VM64 1 "register_operand" "") (match_operand:VM64 2 "register_operand" "") @@ -9255,7 +9285,7 @@ (define_expand "vec_perm<mode>" "TARGET_VIS2" { sparc_expand_vec_perm_bmask (<MODE>mode, operands[3]); - emit_insn (gen_bshuffle<mode>_vis (operands[0], operands[1], operands[2])); + emit_insn (gen_bshuffle<VM64:mode>_vis (operands[0], operands[1], operands[2])); DONE; }) @@ -9360,7 +9390,7 @@ (define_code_attr vis3_shift_insn (define_code_attr vis3_shift_patname [(ashift "ashl") (ss_ashift "ssashl") (lshiftrt "lshr") (ashiftrt "ashr")]) -(define_insn "v<vis3_shift_patname><mode>3" +(define_insn "v<vis3_shift_patname><GCM:mode>3" [(set (match_operand:GCM 0 "register_operand" "=<vconstr>") (vis3_shift:GCM (match_operand:GCM 1 "register_operand" "<vconstr>") (match_operand:GCM 2 "register_operand" "<vconstr>")))] @@ -9368,7 +9398,7 @@ (define_insn "v<vis3_shift_patname><mode "<vis3_shift_insn><vbits>\t%1, %2, %0" [(set_attr "type" "fga")]) -(define_insn "pdistn<mode>_vis" +(define_insn "pdistn<P:mode>_vis" [(set (match_operand:P 0 "register_operand" "=r") (unspec:P [(match_operand:V8QI 1 "register_operand" "e") (match_operand:V8QI 2 "register_operand" "e")] @@ -9419,7 +9449,7 @@ (define_code_attr vis3_addsub_ss_insn (define_code_attr vis3_addsub_ss_patname [(ss_plus "ssadd") (ss_minus "sssub")]) -(define_insn "<vis3_addsub_ss_patname><mode>3" +(define_insn "<vis3_addsub_ss_patname><VASS:mode>3" [(set (match_operand:VASS 0 "register_operand" "=<vconstr>") (vis3_addsub_ss:VASS (match_operand:VASS 1 "register_operand" "<vconstr>") (match_operand:VASS 2 "register_operand" "<vconstr>")))] @@ -9435,7 +9465,7 @@ (define_code_attr vis4_minmax_insn (define_code_attr vis4_minmax_patname [(smin "min") (smax "max")]) -(define_insn "<vis4_minmax_patname><mode>3" +(define_insn "<vis4_minmax_patname><VMMAX:mode>3" [(set (match_operand:VMMAX 0 "register_operand" "=<vconstr>") (vis4_minmax:VMMAX (match_operand:VMMAX 1 "register_operand" "<vconstr>") (match_operand:VMMAX 2 "register_operand" "<vconstr>")))] @@ -9449,7 +9479,7 @@ (define_code_attr vis4_uminmax_insn (define_code_attr vis4_uminmax_patname [(umin "minu") (umax "maxu")]) -(define_insn "<vis4_uminmax_patname><mode>3" +(define_insn "<vis4_uminmax_patname><VMMAX:mode>3" [(set (match_operand:VMMAX 0 "register_operand" "=<vconstr>") (vis4_uminmax:VMMAX (match_operand:VMMAX 1 "register_operand" "<vconstr>") (match_operand:VMMAX 2 "register_operand" "<vconstr>")))] @@ -9474,7 +9504,7 @@ (define_code_attr vis4_addsub_us_insn (define_code_attr vis4_addsub_us_patname [(us_plus "usadd") (us_minus "ussub")]) -(define_insn "<vis4_addsub_us_patname><mode>3" +(define_insn "<vis4_addsub_us_patname><VAUS:mode>3" [(set (match_operand:VAUS 0 "register_operand" "=<vconstr>") (vis4_addsub_us:VAUS (match_operand:VAUS 1 "register_operand" "<vconstr>") (match_operand:VAUS 2 "register_operand" "<vconstr>")))] @@ -9482,23 +9512,23 @@ (define_insn "<vis4_addsub_us_patname><m "<vis4_addsub_us_insn><vbits>\t%1, %2, %0" [(set_attr "type" "fga")]) -(define_insn "fucmp<code>8<P:mode>_vis" +(define_insn "fucmp<gcond:code>8<P:mode>_vis" [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e") + (unspec:P [(gcond:V8QI (match_operand:V8QI 1 "register_operand" "e") (match_operand:V8QI 2 "register_operand" "e"))] UNSPEC_FUCMP))] "TARGET_VIS3" - "fucmp<code>8\t%1, %2, %0" + "fucmp<gcond:code>8\t%1, %2, %0" [(set_attr "type" "visl") (set_attr "v3pipe" "true")]) -(define_insn "fpcmpu<code><GCM:gcm_name><P:mode>_vis" +(define_insn "fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis" [(set (match_operand:P 0 "register_operand" "=r") - (unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e") + (unspec:P [(gcond:GCM (match_operand:GCM 1 "register_operand" "e") (match_operand:GCM 2 "register_operand" "e"))] UNSPEC_FUCMP))] "TARGET_VIS4" - "fpcmpu<code><GCM:gcm_name>\t%1, %2, %0" + "fpcmpu<gcond:code><GCM:gcm_name>\t%1, %2, %0" [(set_attr "type" "visl") (set_attr "fptype" "double")])

[SPARC] Housekeeping work

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