| Message ID | 20240509073300.4968-1-cuiyunhui@bytedance.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v5,1/3] riscv: cacheinfo: remove the useless input parameter (node) of ci_leaf_init() | expand |
Hi, On 5/9/24 02:32, Yunhui Cui wrote: > Before cacheinfo can be built correctly, we need to initialize level > and type. Since RISC-V currently does not have a register group that > describes cache-related attributes like ARM64, we cannot obtain them > directly, so now we obtain cache leaves from the ACPI PPTT table > (acpi_get_cache_info()) and set the cache type through split_levels. > > Suggested-by: Jeremy Linton <jeremy.linton@arm.com> > Suggested-by: Sudeep Holla <sudeep.holla@arm.com> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com> > --- > arch/riscv/kernel/cacheinfo.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c > index 30a6878287ad..d6c108c50cba 100644 > --- a/arch/riscv/kernel/cacheinfo.c > +++ b/arch/riscv/kernel/cacheinfo.c > @@ -3,6 +3,7 @@ > * Copyright (C) 2017 SiFive > */ > > +#include <linux/acpi.h> > #include <linux/cpu.h> > #include <linux/of.h> > #include <asm/cacheinfo.h> > @@ -78,6 +79,27 @@ int populate_cache_leaves(unsigned int cpu) > struct device_node *prev = NULL; > int levels = 1, level = 1; > > + if (!acpi_disabled) { > + int ret, fw_levels, split_levels; > + > + ret = acpi_get_cache_info(cpu, &fw_levels, &split_levels); > + if (ret) > + return ret; > + > + BUG_ON((split_levels > fw_levels) || > + (split_levels + fw_levels > this_cpu_ci->num_leaves)); > + > + for (; level <= this_cpu_ci->num_levels; level++) { > + if (level <= split_levels) { > + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); > + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); > + } else { > + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); > + } > + } > + return 0; > + } > + > if (of_property_read_bool(np, "cache-size")) > ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); > if (of_property_read_bool(np, "i-cache-size")) Yes, still looks good. Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> Thanks,
Hi Palmer, There are already related Reviewed-by, Gentle ping... On Thu, May 9, 2024 at 11:27 PM Sudeep Holla <sudeep.holla@arm.com> wrote: > > On Thu, May 09, 2024 at 03:32:59PM +0800, Yunhui Cui wrote: > > Before cacheinfo can be built correctly, we need to initialize level > > and type. Since RISC-V currently does not have a register group that > > describes cache-related attributes like ARM64, we cannot obtain them > > directly, so now we obtain cache leaves from the ACPI PPTT table > > (acpi_get_cache_info()) and set the cache type through split_levels. > > > > Suggested-by: Jeremy Linton <jeremy.linton@arm.com> > > Suggested-by: Sudeep Holla <sudeep.holla@arm.com> > > I am not sure why you have not added my reviewed-by as I was happy with > v3 onwards IIRC. Anyways, I will give it again 😄 > > Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> > > -- > Regards, > Sudeep Thanks， Yunhui
Hi Palmer, Gentle ping ... On Fri, May 10, 2024 at 5:09 PM yunhui cui <cuiyunhui@bytedance.com> wrote: > > Hi Palmer, > > There are already related Reviewed-by, Gentle ping... > > On Thu, May 9, 2024 at 11:27 PM Sudeep Holla <sudeep.holla@arm.com> wrote: > > > > On Thu, May 09, 2024 at 03:32:59PM +0800, Yunhui Cui wrote: > > > Before cacheinfo can be built correctly, we need to initialize level > > > and type. Since RISC-V currently does not have a register group that > > > describes cache-related attributes like ARM64, we cannot obtain them > > > directly, so now we obtain cache leaves from the ACPI PPTT table > > > (acpi_get_cache_info()) and set the cache type through split_levels. > > > > > > Suggested-by: Jeremy Linton <jeremy.linton@arm.com> > > > Suggested-by: Sudeep Holla <sudeep.holla@arm.com> > > > > I am not sure why you have not added my reviewed-by as I was happy with > > v3 onwards IIRC. Anyways, I will give it again 😄 > > > > Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> > > > > -- > > Regards, > > Sudeep > > Thanks， > Yunhui Thanks, Yunhui
diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c index 09e9b88110d1..30a6878287ad 100644 --- a/arch/riscv/kernel/cacheinfo.c +++ b/arch/riscv/kernel/cacheinfo.c @@ -64,7 +64,6 @@ uintptr_t get_cache_geometry(u32 level, enum cache_type type) } static void ci_leaf_init(struct cacheinfo *this_leaf, - struct device_node *node, enum cache_type type, unsigned int level) { this_leaf->level = level; @@ -80,11 +79,11 @@ int populate_cache_leaves(unsigned int cpu) int levels = 1, level = 1; if (of_property_read_bool(np, "cache-size")) - ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); if (of_property_read_bool(np, "i-cache-size")) - ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); if (of_property_read_bool(np, "d-cache-size")) - ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); prev = np; while ((np = of_find_next_cache_node(np))) { @@ -97,11 +96,11 @@ int populate_cache_leaves(unsigned int cpu) if (level <= levels) break; if (of_property_read_bool(np, "cache-size")) - ci_leaf_init(this_leaf++, np, CACHE_TYPE_UNIFIED, level); + ci_leaf_init(this_leaf++, CACHE_TYPE_UNIFIED, level); if (of_property_read_bool(np, "i-cache-size")) - ci_leaf_init(this_leaf++, np, CACHE_TYPE_INST, level); + ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); if (of_property_read_bool(np, "d-cache-size")) - ci_leaf_init(this_leaf++, np, CACHE_TYPE_DATA, level); + ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); levels = level; } of_node_put(np);
ci_leaf_init() is a declared static function. The implementation of the function body and the caller do not use the parameter (struct device_node *node) input parameter, so remove it. Fixes: 6a24915145c9 ("Revert "riscv: Set more data to cacheinfo"") Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> --- arch/riscv/kernel/cacheinfo.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-)