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[Linaro-uefi] D02: Add two package at DSDT table

Message ID 1477542266-118914-1-git-send-email-heyi.guo@linaro.org
State Accepted
Commit d21140336f862d713c2074c9cc34566272283984
Headers show

Commit Message

gary guo Oct. 27, 2016, 4:24 a.m. UTC 
com.asl: add reg-io-width and reg-shift package,
for kernel using to set com port.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
 Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl | 2 ++
 1 file changed, 2 insertions(+)

Comments

Ard Biesheuvel Oct. 28, 2016, 12:06 p.m. UTC | #1 
On 27 October 2016 at 05:24, Heyi Guo <heyi.guo@linaro.org> wrote:
> com.asl: add reg-io-width and reg-shift package,
> for kernel using to set com port.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>

Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Pushed, thanks.

> ---
>  Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl
> index 3bcc5fb..e3fc0d3 100644
> --- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl
> +++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl
> @@ -30,6 +30,8 @@ Scope(_SB)
>        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
>        Package () {
>          Package () {"clock-frequency", 200000000},
> +        Package () {"reg-io-width", 4},
> +        Package () {"reg-shift", 2},
>        }
>      })
>    }
> --
> 1.9.1
>
diff mbox

Patch

diff --git a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl
index 3bcc5fb..e3fc0d3 100644
--- a/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl
+++ b/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/Com.asl
@@ -30,6 +30,8 @@  Scope(_SB)
       ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
       Package () {
         Package () {"clock-frequency", 200000000},
+        Package () {"reg-io-width", 4},
+        Package () {"reg-shift", 2},
       }
     })
   }