From patchwork Thu Oct 27 14:47:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 79689 Delivered-To: patch@linaro.org Received: by 10.80.142.83 with SMTP id 19csp685462edx; Thu, 27 Oct 2016 07:47:53 -0700 (PDT) X-Received: by 10.28.94.139 with SMTP id s133mr8870144wmb.1.1477579673163; Thu, 27 Oct 2016 07:47:53 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id k3si3651394wme.37.2016.10.27.07.47.52; Thu, 27 Oct 2016 07:47:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2CFDCA7549; Thu, 27 Oct 2016 16:47:45 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id O7DCG8bglsIj; Thu, 27 Oct 2016 16:47:45 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1AB0EA754C; Thu, 27 Oct 2016 16:47:40 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 013FF4B9F9 for ; Thu, 27 Oct 2016 16:47:33 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id t5mNqrwLrTbm for ; Thu, 27 Oct 2016 16:47:32 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg-07.nifty.com (conuserg-07.nifty.com [210.131.2.74]) by theia.denx.de (Postfix) with ESMTPS id 2B2A44B624 for ; Thu, 27 Oct 2016 16:47:29 +0200 (CEST) Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id u9RElDVJ017011; Thu, 27 Oct 2016 23:47:20 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com u9RElDVJ017011 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1477579640; bh=i84cg5ny0QTDGagnX6nNaH0T5nqDAevJU34Ka00PFEA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=zSoxZyQCpngfrY/tLfo3+KdARsitVbpsAsBxQzWVTKNO48tfklCdBIUZIc0lb4Ltn ALn6MR9m3u3IoQ5448GtcLWG0OdjheSPE+YHlnxqcGxqRUPsY1B+rQ6vUFIqHjkS/1 u9v7YP4wYKuXbsOxP/SoS4aQIkGAWxkVfOgiOL5iJIzaX2O6RAZb63fkcyQYDwXFp1 M+2eeNu0N3dLV8pRMCWBlsxkfvWvE7NIT4Y7sVorXLgANSWdedMfpaggNxDLVGn0ss ODET1oMg5aIUEnDJ3oPYwaM84WS94jL1ldncLiUNH3ZNx9t6vdszYmwHyDTnpMM4eY BL6belndw50nw== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Thu, 27 Oct 2016 23:47:00 +0900 Message-Id: <1477579630-9692-2-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1477579630-9692-1-git-send-email-yamada.masahiro@socionext.com> References: <1477579630-9692-1-git-send-email-yamada.masahiro@socionext.com> Cc: Albert Aribaud Subject: [U-Boot] [PATCH 01/11] ARM: uniphier: enable SSC for more PLLs for LD20 SoC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" For Electro-Magnetic Compatibility. Set CPLL, SPLL2, MPLL, VPPLL, GPPLL, DPLL* to SSC rate 1 percent. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/clk/dpll-ld20.c | 9 +++------ arch/arm/mach-uniphier/clk/pll-ld20.c | 15 ++++++++------- 2 files changed, 11 insertions(+), 13 deletions(-) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-uniphier/clk/dpll-ld20.c b/arch/arm/mach-uniphier/clk/dpll-ld20.c index 1132313..86e99c4 100644 --- a/arch/arm/mach-uniphier/clk/dpll-ld20.c +++ b/arch/arm/mach-uniphier/clk/dpll-ld20.c @@ -11,12 +11,9 @@ int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd) { - unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags); - unsigned int dram_freq = bd->dram_freq; - - uniphier_ld20_sscpll_init(SC_DPLL0CTRL, dram_freq, dpll_ssc_rate, 2); - uniphier_ld20_sscpll_init(SC_DPLL1CTRL, dram_freq, dpll_ssc_rate, 2); - uniphier_ld20_sscpll_init(SC_DPLL2CTRL, dram_freq, dpll_ssc_rate, 2); + uniphier_ld20_sscpll_init(SC_DPLL0CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_DPLL1CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); + uniphier_ld20_sscpll_init(SC_DPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); return 0; } diff --git a/arch/arm/mach-uniphier/clk/pll-ld20.c b/arch/arm/mach-uniphier/clk/pll-ld20.c index 5e545da..8ad6883 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld20.c +++ b/arch/arm/mach-uniphier/clk/pll-ld20.c @@ -13,8 +13,6 @@ int uniphier_ld20_pll_init(const struct uniphier_board_data *bd) { - unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags); - uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); /* do nothing for SPLL */ uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); @@ -24,11 +22,14 @@ int uniphier_ld20_pll_init(const struct uniphier_board_data *bd) mdelay(1); - if (dpll_ssc_rate > 0) { - uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL); - uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL); - uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL); - } + uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL); + uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_GPPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL); uniphier_ld20_vpll27_init(SC_VPLL27FCTRL); uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);