[v2,17/37] target/sparc: Implement FPADD64, FPSUB64

Message ID	20240526194254.459395-18-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> Subject: [PATCH v2 17/37] target/sparc: Implement FPADD64, FPSUB64 Date: Sun, 26 May 2024 12:42:34 -0700 Message-Id: <20240526194254.459395-18-richard.henderson@linaro.org> In-Reply-To: <20240526194254.459395-1-richard.henderson@linaro.org> References: <20240526194254.459395-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	target/sparc: Implement VIS4 \| expand [v2,00/37] target/sparc: Implement VIS4 [v2,01/37] target/sparc: Fix ARRAY8 [v2,02/37] target/sparc: Rewrite gen_edge [v2,03/37] target/sparc: Fix do_dc [v2,04/37] target/sparc: Fix helper_fmul8ulx16 [v2,05/37] target/sparc: Perform DFPREG/QFPREG in decodetree [v2,06/37] target/sparc: Remove gen_dest_fpr_D [v2,07/37] target/sparc: Remove cpu_fpr[] [v2,08/37] target/sparc: Use gvec for VIS1 parallel add/sub [v2,09/37] target/sparc: Implement FMAf extension [v2,10/37] target/sparc: Add feature bits for VIS 3 [v2,11/37] target/sparc: Implement ADDXC, ADDXCcc [v2,12/37] target/sparc: Implement CMASK instructions [v2,13/37] target/sparc: Implement FCHKSM16 [v2,14/37] target/sparc: Implement FHADD, FHSUB, FNHADD, FNADD, FNMUL [v2,15/37] target/sparc: Implement FLCMP [v2,16/37] target/sparc: Implement FMEAN16 [v2,17/37] target/sparc: Implement FPADD64, FPSUB64 [v2,18/37] target/sparc: Implement FPADDS, FPSUBS [v2,19/37] target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8 [v2,20/37] target/sparc: Implement FSLL, FSRL, FSRA, FSLAS [v2,21/37] target/sparc: Implement LDXEFSR [v2,22/37] target/sparc: Implement LZCNT [v2,23/37] target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd [v2,24/37] target/sparc: Implement PDISTN [v2,25/37] target/sparc: Implement UMULXHI [v2,26/37] target/sparc: Implement XMULX [v2,27/37] target/sparc: Enable VIS3 feature bit [v2,28/37] target/sparc: Implement IMA extension [v2,29/37] target/sparc: Add feature bit for VIS4 [v2,30/37] target/sparc: Implement FALIGNDATAi [v2,31/37] target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS [v2,32/37] target/sparc: Implement VIS4 comparisons [v2,33/37] target/sparc: Implement FPMIN, FPMAX [v2,34/37] target/sparc: Implement SUBXC, SUBXCcc [v2,35/37] target/sparc: Implement MWAIT [v2,36/37] target/sparc: Implement monitor ASIs [v2,37/37] target/sparc: Enable VIS4 feature bit

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20240526194254.459395-18-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk,
 =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>
Subject: [PATCH v2 17/37] target/sparc: Implement FPADD64, FPSUB64
Date: Sun, 26 May 2024 12:42:34 -0700
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Series

target/sparc: Implement VIS4 | expand

Commit Message

Richard Henderson May 26, 2024, 7:42 p.m. UTC

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/insns.decode | 2 ++
 target/sparc/translate.c  | 3 +++
 2 files changed, 5 insertions(+)

diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index febd1a4a13..70ca41a69a 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -441,10 +441,12 @@  FCMPEq      10 000 cc:2 110101 .....  0 0101 0111 .....    \
     FPADD16s    10 ..... 110110 ..... 0 0101 0001 .....    @r_r_r
     FPADD32     10 ..... 110110 ..... 0 0101 0010 .....    @d_d_d
     FPADD32s    10 ..... 110110 ..... 0 0101 0011 .....    @r_r_r
+    FPADD64     10 ..... 110110 ..... 0 0100 0010 .....    @d_d_d
     FPSUB16     10 ..... 110110 ..... 0 0101 0100 .....    @d_d_d
     FPSUB16s    10 ..... 110110 ..... 0 0101 0101 .....    @r_r_r
     FPSUB32     10 ..... 110110 ..... 0 0101 0110 .....    @d_d_d
     FPSUB32s    10 ..... 110110 ..... 0 0101 0111 .....    @r_r_r
+    FPSUB64     10 ..... 110110 ..... 0 0100 0110 .....    @d_d_d
 
     FNORd       10 ..... 110110 ..... 0 0110 0010 .....    @d_d_d
     FNORs       10 ..... 110110 ..... 0 0110 0011 .....    @r_r_r
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index cf5f1ea4d0..52b9590b4b 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4908,6 +4908,9 @@  TRANS(FHADDd, VIS3, do_ddd, a, gen_op_fhaddd)
 TRANS(FHSUBd, VIS3, do_ddd, a, gen_op_fhsubd)
 TRANS(FNHADDd, VIS3, do_ddd, a, gen_op_fnhaddd)
 
+TRANS(FPADD64, VIS3B, do_ddd, a, tcg_gen_add_i64)
+TRANS(FPSUB64, VIS3B, do_ddd, a, tcg_gen_sub_i64)
+
 static bool do_rdd(DisasContext *dc, arg_r_r_r *a,
                    void (*func)(TCGv, TCGv_i64, TCGv_i64))
 {

[v2,17/37] target/sparc: Implement FPADD64, FPSUB64

Commit Message

Patch