diff mbox series

[v3,02/15] pinctrl: renesas: pinctrl-rzg2l: Rename B0WI to BOWI

Message ID 20240530173857.164073-3-prabhakar.mahadev-lad.rj@bp.renesas.com
State New
Headers show
Series Add PFC support for Renesas RZ/V2H(P) SoC | expand

Commit Message

Prabhakar May 30, 2024, 5:38 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Fix the typo B0WI -> BOWI to match with the RZ/G2L HW manual.

Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3
- New patch
---
 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

Comments

Geert Uytterhoeven June 5, 2024, 11:39 a.m. UTC | #1 
Hi Prabhakar,

On Thu, May 30, 2024 at 7:41 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Fix the typo B0WI -> BOWI to match with the RZ/G2L HW manual.
>
> Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3
> - New patch

Thanks for your patch!

I had a deeper look, as the name "B0WI" (with zero) is also present
in drivers/pinctrl/renesas/pinctrl-rza2.c, and because Section 41.4.2
("Operation for Peripheral Function") in the RZ/G2L Group Hardware
User's Manual does talk about the "B0WI" (with zero) bit.

Apparently Rev. 0.51 of the RZ/A2M Group Hardware User's Manual used
both variants. Later (Rev. 1.00) revisions replaced the O-based
variant by the zero-based variant. So it looks like "B0WI" (with
zero) is correct, and the RZ/G2L, RZ/V2L, RZ/G2UL, and RZ/Five HW
manuals should be fixed instead. The RZ/G3S manual already uses
the correct naming.

Gr{oetje,eeting}s,

                        Geert
Prabhakar June 5, 2024, 3:42 p.m. UTC | #2 
Hi Geert,

Thank you for the review.

On Wed, Jun 5, 2024 at 12:39 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Thu, May 30, 2024 at 7:41 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Fix the typo B0WI -> BOWI to match with the RZ/G2L HW manual.
> >
> > Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v2->v3
> > - New patch
>
> Thanks for your patch!
>
> I had a deeper look, as the name "B0WI" (with zero) is also present
> in drivers/pinctrl/renesas/pinctrl-rza2.c, and because Section 41.4.2
> ("Operation for Peripheral Function") in the RZ/G2L Group Hardware
> User's Manual does talk about the "B0WI" (with zero) bit.
>
> Apparently Rev. 0.51 of the RZ/A2M Group Hardware User's Manual used
> both variants. Later (Rev. 1.00) revisions replaced the O-based
> variant by the zero-based variant. So it looks like "B0WI" (with
> zero) is correct, and the RZ/G2L, RZ/V2L, RZ/G2UL, and RZ/Five HW
> manuals should be fixed instead. The RZ/G3S manual already uses
> the correct naming.
>
Ok I'll drop this patch and create a request with the HW manual team
to correct it.

Cheers,
Prabhakar
diff mbox series

Patch

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index f784169abf11..169986022a73 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -131,7 +131,7 @@ 
 #define PVDD_1800		1	/* I/O domain voltage <= 1.8V */
 #define PVDD_3300		0	/* I/O domain voltage >= 3.3V */
 
-#define PWPR_B0WI		BIT(7)	/* Bit Write Disable */
+#define PWPR_BOWI		BIT(7)	/* Bit Write Disable */
 #define PWPR_PFCWE		BIT(6)	/* PFC Register Write Enable */
 
 #define PM_MASK			0x03
@@ -478,8 +478,8 @@  static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
 	writeb(reg & ~BIT(pin), pctrl->base + PMC(off));
 
 	/* Set the PWPR register to allow PFC register to write */
-	writel(0x0, pctrl->base + regs->pwpr);		/* B0WI=0, PFCWE=0 */
-	writel(PWPR_PFCWE, pctrl->base + regs->pwpr);	/* B0WI=0, PFCWE=1 */
+	writel(0x0, pctrl->base + regs->pwpr);		/* BOWI=0, PFCWE=0 */
+	writel(PWPR_PFCWE, pctrl->base + regs->pwpr);	/* BOWI=0, PFCWE=1 */
 
 	/* Select Pin function mode with PFC register */
 	reg = readl(pctrl->base + PFC(off));
@@ -487,8 +487,8 @@  static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
 	writel(reg | (func << (pin * 4)), pctrl->base + PFC(off));
 
 	/* Set the PWPR register to be write-protected */
-	writel(0x0, pctrl->base + regs->pwpr);		/* B0WI=0, PFCWE=0 */
-	writel(PWPR_B0WI, pctrl->base + regs->pwpr);	/* B0WI=1, PFCWE=0 */
+	writel(0x0, pctrl->base + regs->pwpr);		/* BOWI=0, PFCWE=0 */
+	writel(PWPR_BOWI, pctrl->base + regs->pwpr);	/* BOWI=1, PFCWE=0 */
 
 	/* Switch to Peripheral pin function with PMC register */
 	reg = readb(pctrl->base + PMC(off));
@@ -2520,8 +2520,8 @@  static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
 	const struct rzg2l_register_offsets *regs = &hwcfg->regs;
 
 	/* Set the PWPR register to allow PFC register to write. */
-	writel(0x0, pctrl->base + regs->pwpr);		/* B0WI=0, PFCWE=0 */
-	writel(PWPR_PFCWE, pctrl->base + regs->pwpr);	/* B0WI=0, PFCWE=1 */
+	writel(0x0, pctrl->base + regs->pwpr);		/* BOWI=0, PFCWE=0 */
+	writel(PWPR_PFCWE, pctrl->base + regs->pwpr);	/* BOWI=0, PFCWE=1 */
 
 	/* Restore port registers. */
 	for (u32 port = 0; port < nports; port++) {
@@ -2565,8 +2565,8 @@  static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
 	}
 
 	/* Set the PWPR register to be write-protected. */
-	writel(0x0, pctrl->base + regs->pwpr);		/* B0WI=0, PFCWE=0 */
-	writel(PWPR_B0WI, pctrl->base + regs->pwpr);	/* B0WI=1, PFCWE=0 */
+	writel(0x0, pctrl->base + regs->pwpr);		/* BOWI=0, PFCWE=0 */
+	writel(PWPR_BOWI, pctrl->base + regs->pwpr);	/* BOWI=1, PFCWE=0 */
 }
 
 static int rzg2l_pinctrl_suspend_noirq(struct device *dev)