| Message ID | 20240612-sa8775p-v2-gcc-gpucc-fixes-v2-3-adcc756a23df@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Update GCC, GPUCC clock drivers on SA8775P | expand |
On 6/12/24 13:08, Taniya Das wrote: > Update the force mem core bit for UFS ICE clock to force the core on > signal to remain active during halt state of the clk. If force mem > core bit of the clock is not set, the memories of the subsystem will > not retain the logic across power states. > > Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p") > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c index 71fa95f59a0a..23b5207dc606 100644 --- a/drivers/clk/qcom/gcc-sa8775p.c +++ b/drivers/clk/qcom/gcc-sa8775p.c @@ -4686,6 +4686,9 @@ static int gcc_sa8775p_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */ + /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ + qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); + return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap); }
Update the force mem core bit for UFS ICE clock to force the core on signal to remain active during halt state of the clk. If force mem core bit of the clock is not set, the memories of the subsystem will not retain the logic across power states. Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> --- drivers/clk/qcom/gcc-sa8775p.c | 3 +++ 1 file changed, 3 insertions(+)