| Message ID | 20240619113529.676940-9-cleger@rivosinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for a few Zc* extensions, Zcmop and Zimop | expand |
On Wed, Jun 19, 2024 at 01:35:18PM +0200, Clément Léger wrote: > The Zc* standard extension for code reduction introduces new extensions. > This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp > are left out of this patch since they are targeting microcontrollers/ > embedded CPUs instead of application processors. > > Signed-off-by: Clément Léger <cleger@rivosinc.com> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > --- > arch/riscv/include/asm/hwcap.h | 4 +++ > arch/riscv/kernel/cpufeature.c | 55 +++++++++++++++++++++++++++++++++- > 2 files changed, 58 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 18859277843a..b12ae3f2141c 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -87,6 +87,10 @@ > #define RISCV_ISA_EXT_ZVE64F 78 > #define RISCV_ISA_EXT_ZVE64D 79 > #define RISCV_ISA_EXT_ZIMOP 80 > +#define RISCV_ISA_EXT_ZCA 81 > +#define RISCV_ISA_EXT_ZCB 82 > +#define RISCV_ISA_EXT_ZCD 83 > +#define RISCV_ISA_EXT_ZCF 84 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index a3af976f36c9..aa631fe49b7c 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -111,6 +111,9 @@ static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data, > > #define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, NULL) > > +#define __RISCV_ISA_EXT_DATA_VALIDATE(_name, _id, _validate) \ > + _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, _validate) > + > /* Used to declare pure "lasso" extension (Zk for instance) */ > #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ > _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, \ > @@ -122,6 +125,37 @@ static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data, > #define __RISCV_ISA_EXT_SUPERSET_VALIDATE(_name, _id, _sub_exts, _validate) \ > _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), _validate) > > +static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data, It's super minor, but my OCD doesn't like this being called "depends" when the others are all called "validate". > + const unsigned long *isa_bitmap) > +{ > + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA)) > + return 0; > + > + return -EPROBE_DEFER; > +} > +static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data, > + const unsigned long *isa_bitmap) > +{ > + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && > + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) > + return 0; > + > + return -EPROBE_DEFER; > +} > + > +static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data, > + const unsigned long *isa_bitmap) > +{ > + if (IS_ENABLED(CONFIG_64BIT)) > + return -EINVAL; > + > + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && > + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) > + return 0; > + > + return -EPROBE_DEFER; > +}
On 23/06/2024 17:42, Conor Dooley wrote: > On Wed, Jun 19, 2024 at 01:35:18PM +0200, Clément Léger wrote: >> The Zc* standard extension for code reduction introduces new extensions. >> This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp >> are left out of this patch since they are targeting microcontrollers/ >> embedded CPUs instead of application processors. >> >> Signed-off-by: Clément Léger <cleger@rivosinc.com> >> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> >> --- >> arch/riscv/include/asm/hwcap.h | 4 +++ >> arch/riscv/kernel/cpufeature.c | 55 +++++++++++++++++++++++++++++++++- >> 2 files changed, 58 insertions(+), 1 deletion(-) >> >> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h >> index 18859277843a..b12ae3f2141c 100644 >> --- a/arch/riscv/include/asm/hwcap.h >> +++ b/arch/riscv/include/asm/hwcap.h >> @@ -87,6 +87,10 @@ >> #define RISCV_ISA_EXT_ZVE64F 78 >> #define RISCV_ISA_EXT_ZVE64D 79 >> #define RISCV_ISA_EXT_ZIMOP 80 >> +#define RISCV_ISA_EXT_ZCA 81 >> +#define RISCV_ISA_EXT_ZCB 82 >> +#define RISCV_ISA_EXT_ZCD 83 >> +#define RISCV_ISA_EXT_ZCF 84 >> >> #define RISCV_ISA_EXT_XLINUXENVCFG 127 >> >> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >> index a3af976f36c9..aa631fe49b7c 100644 >> --- a/arch/riscv/kernel/cpufeature.c >> +++ b/arch/riscv/kernel/cpufeature.c >> @@ -111,6 +111,9 @@ static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data, >> >> #define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, NULL) >> >> +#define __RISCV_ISA_EXT_DATA_VALIDATE(_name, _id, _validate) \ >> + _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, _validate) >> + >> /* Used to declare pure "lasso" extension (Zk for instance) */ >> #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ >> _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, \ >> @@ -122,6 +125,37 @@ static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data, >> #define __RISCV_ISA_EXT_SUPERSET_VALIDATE(_name, _id, _sub_exts, _validate) \ >> _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), _validate) >> >> +static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data, > > It's super minor, but my OCD doesn't like this being called "depends" > when the others are all called "validate". Ok, let's make a deal. You review patch 14/16 and I'll make the machine part of you happy and call this function validate ;) Thanks, Clément > >> + const unsigned long *isa_bitmap) >> +{ >> + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA)) >> + return 0; >> + >> + return -EPROBE_DEFER; >> +} >> +static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data, >> + const unsigned long *isa_bitmap) >> +{ >> + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && >> + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) >> + return 0; >> + >> + return -EPROBE_DEFER; >> +} >> + >> +static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data, >> + const unsigned long *isa_bitmap) >> +{ >> + if (IS_ENABLED(CONFIG_64BIT)) >> + return -EINVAL; >> + >> + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && >> + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) >> + return 0; >> + >> + return -EPROBE_DEFER; >> +}
On Mon, Jun 24, 2024 at 10:24:51AM +0200, Clément Léger wrote: > > > On 23/06/2024 17:42, Conor Dooley wrote: > > On Wed, Jun 19, 2024 at 01:35:18PM +0200, Clément Léger wrote: > >> The Zc* standard extension for code reduction introduces new extensions. > >> This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp > >> are left out of this patch since they are targeting microcontrollers/ > >> embedded CPUs instead of application processors. > >> > >> Signed-off-by: Clément Léger <cleger@rivosinc.com> > >> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > >> --- > >> arch/riscv/include/asm/hwcap.h | 4 +++ > >> arch/riscv/kernel/cpufeature.c | 55 +++++++++++++++++++++++++++++++++- > >> 2 files changed, 58 insertions(+), 1 deletion(-) > >> > >> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > >> index 18859277843a..b12ae3f2141c 100644 > >> --- a/arch/riscv/include/asm/hwcap.h > >> +++ b/arch/riscv/include/asm/hwcap.h > >> @@ -87,6 +87,10 @@ > >> #define RISCV_ISA_EXT_ZVE64F 78 > >> #define RISCV_ISA_EXT_ZVE64D 79 > >> #define RISCV_ISA_EXT_ZIMOP 80 > >> +#define RISCV_ISA_EXT_ZCA 81 > >> +#define RISCV_ISA_EXT_ZCB 82 > >> +#define RISCV_ISA_EXT_ZCD 83 > >> +#define RISCV_ISA_EXT_ZCF 84 > >> > >> #define RISCV_ISA_EXT_XLINUXENVCFG 127 > >> > >> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > >> index a3af976f36c9..aa631fe49b7c 100644 > >> --- a/arch/riscv/kernel/cpufeature.c > >> +++ b/arch/riscv/kernel/cpufeature.c > >> @@ -111,6 +111,9 @@ static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data, > >> > >> #define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, NULL) > >> > >> +#define __RISCV_ISA_EXT_DATA_VALIDATE(_name, _id, _validate) \ > >> + _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, _validate) > >> + > >> /* Used to declare pure "lasso" extension (Zk for instance) */ > >> #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ > >> _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, \ > >> @@ -122,6 +125,37 @@ static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data, > >> #define __RISCV_ISA_EXT_SUPERSET_VALIDATE(_name, _id, _sub_exts, _validate) \ > >> _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), _validate) > >> > >> +static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data, > > > > It's super minor, but my OCD doesn't like this being called "depends" > > when the others are all called "validate". > > Ok, let's make a deal. You review patch 14/16 and I'll make the machine > part of you happy and call this function validate ;) I generally avoid the hwprobe patches intentionally :) I'm not even expecting a respin for this tbh, I'd like to just get it in so that I can do things on top of it.
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 18859277843a..b12ae3f2141c 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -87,6 +87,10 @@ #define RISCV_ISA_EXT_ZVE64F 78 #define RISCV_ISA_EXT_ZVE64D 79 #define RISCV_ISA_EXT_ZIMOP 80 +#define RISCV_ISA_EXT_ZCA 81 +#define RISCV_ISA_EXT_ZCB 82 +#define RISCV_ISA_EXT_ZCD 83 +#define RISCV_ISA_EXT_ZCF 84 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index a3af976f36c9..aa631fe49b7c 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -111,6 +111,9 @@ static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data, #define __RISCV_ISA_EXT_DATA(_name, _id) _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, NULL) +#define __RISCV_ISA_EXT_DATA_VALIDATE(_name, _id, _validate) \ + _RISCV_ISA_EXT_DATA(_name, _id, NULL, 0, _validate) + /* Used to declare pure "lasso" extension (Zk for instance) */ #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, \ @@ -122,6 +125,37 @@ static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data, #define __RISCV_ISA_EXT_SUPERSET_VALIDATE(_name, _id, _sub_exts, _validate) \ _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), _validate) +static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA)) + return 0; + + return -EPROBE_DEFER; +} +static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) + return 0; + + return -EPROBE_DEFER; +} + +static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (IS_ENABLED(CONFIG_64BIT)) + return -EINVAL; + + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) + return 0; + + return -EPROBE_DEFER; +} + static const unsigned int riscv_zk_bundled_exts[] = { RISCV_ISA_EXT_ZBKB, RISCV_ISA_EXT_ZBKC, @@ -236,6 +270,21 @@ static const unsigned int riscv_xlinuxenvcfg_exts[] = { RISCV_ISA_EXT_XLINUXENVCFG }; +/* + * Zc* spec states that: + * - C always implies Zca + * - C+F implies Zcf (RV32 only) + * - C+D implies Zcd + * + * These extensions will be enabled and then validated depending on the + * availability of F/D RV32. + */ +static const unsigned int riscv_c_exts[] = { + RISCV_ISA_EXT_ZCA, + RISCV_ISA_EXT_ZCF, + RISCV_ISA_EXT_ZCD, +}; + /* * The canonical order of ISA extension names in the ISA string is defined in * chapter 27 of the unprivileged specification. @@ -282,7 +331,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f), __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), - __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c), + __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts), __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts), __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, @@ -301,6 +350,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), + __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA), + __RISCV_ISA_EXT_DATA_VALIDATE(zcb, RISCV_ISA_EXT_ZCB, riscv_ext_zca_depends), + __RISCV_ISA_EXT_DATA_VALIDATE(zcd, RISCV_ISA_EXT_ZCD, riscv_ext_zcd_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zcf, RISCV_ISA_EXT_ZCF, riscv_ext_zcf_validate), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC),