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(They are equivalent to LDARB, LDARH and LDAR instructions other than the weaker memory ordering requirement.) For more details about weak release consistency see https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions opcodes/ 2016-11-07 Szabolcs Nagy * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr. * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. * aarch64-opc-2.c: Regenerate. gas/testsuite/ 2016-11-07 Szabolcs Nagy * gas/aarch64/ldst-exclusive-armv8_3.s: Add ldaprb, ldaprh, ldapr tests. * gas/aarch64/ldst-exclusive-armv8_3.d: Likewise. * gas/aarch64/illegal-ldapr.s: Likewise. * gas/aarch64/illegal-ldapr.d: Likewise. * gas/aarch64/illegal-ldapr.l: Likewise. diff --git a/gas/testsuite/gas/aarch64/illegal-ldapr.d b/gas/testsuite/gas/aarch64/illegal-ldapr.d new file mode 100644 index 0000000..36e94df --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-ldapr.d @@ -0,0 +1,2 @@ +#as: -march=armv8.3-a -mno-verbose-error +#error-output: illegal-ldapr.l diff --git a/gas/testsuite/gas/aarch64/illegal-ldapr.l b/gas/testsuite/gas/aarch64/illegal-ldapr.l new file mode 100644 index 0000000..f5d85f0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-ldapr.l @@ -0,0 +1,16 @@ +[^:]+: Assembler messages: +[^:]+:18: Error: operand mismatch -- `ldaprb x0,\[x1\]' +[^:]+:19: Error: operand mismatch -- `ldaprh x0,\[x1\]' +[^:]+:20: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr x0,\[x1,#8\]' +[^:]+:24: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprb w1,\[xz\]' +[^:]+:24: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprb w1,\[x7,#8\]' +[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldaprb w1,\[x7,#8\]!' +[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldaprb w1,\[x7\],#8' +[^:]+:24: Error: 64-bit integer or SP register expected at operand 2 -- `ldaprh w1,\[xz\]' +[^:]+:24: Error: the optional immediate offset can only be 0 at operand 2 -- `ldaprh w1,\[x7,#8\]' +[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldaprh w1,\[x7,#8\]!' +[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldaprh w1,\[x7\],#8' +[^:]+:24: Error: 64-bit integer or SP register expected at operand 2 -- `ldapr w1,\[xz\]' +[^:]+:24: Error: the optional immediate offset can only be 0 at operand 2 -- `ldapr w1,\[x7,#8\]' +[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7,#8\]!' +[^:]+:24: Error: invalid addressing mode at operand 2 -- `ldapr w1,\[x7\],#8' diff --git a/gas/testsuite/gas/aarch64/illegal-ldapr.s b/gas/testsuite/gas/aarch64/illegal-ldapr.s new file mode 100644 index 0000000..5943f8b --- /dev/null +++ b/gas/testsuite/gas/aarch64/illegal-ldapr.s @@ -0,0 +1,25 @@ +/* Test illegal ARMv8.3 weaker release consistency load instructions. */ + + /* , [{,#0}] */ + .macro LR32 op + \op w1, [xz] + \op w1, [x7, #8] + \op w1, [x7, #8]! + \op w1, [x7], #8 + .endm + +.text + /* Good. */ + ldaprb w0, [x1] + ldaprh w0, [x1] + ldapr x0, [x1] + + /* Bad. */ + ldaprb x0, [x1] + ldaprh x0, [x1] + ldapr x0, [x1,#8] + + .irp op, ldaprb, ldaprh, ldapr + LR32 \op + .endr + diff --git a/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d b/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d new file mode 100644 index 0000000..b0de88a --- /dev/null +++ b/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.d @@ -0,0 +1,20 @@ +#objdump: -dr +#as: -march=armv8.3-a + +.*: file format .* + +Disassembly of section \.text: + +0000000000000000 <.*>: + 0: 38bfc0e1 ldaprb w1, \[x7\] + 4: 38bfc0e1 ldaprb w1, \[x7\] + 8: 38bfc0e1 ldaprb w1, \[x7\] + c: 78bfc0e1 ldaprh w1, \[x7\] + 10: 78bfc0e1 ldaprh w1, \[x7\] + 14: 78bfc0e1 ldaprh w1, \[x7\] + 18: b8bfc0e1 ldapr w1, \[x7\] + 1c: b8bfc0e1 ldapr w1, \[x7\] + 20: b8bfc0e1 ldapr w1, \[x7\] + 24: f8bfc0e1 ldapr x1, \[x7\] + 28: f8bfc0e1 ldapr x1, \[x7\] + 2c: f8bfc0e1 ldapr x1, \[x7\] diff --git a/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.s b/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.s new file mode 100644 index 0000000..bfa41e0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/ldst-exclusive-armv8_3.s @@ -0,0 +1,22 @@ + /* ARMv8.3 weaker release consistency load instructions. */ + + /* , [{,#0}] */ + .macro LR32 op + \op w1, [x7] + \op w1, [x7, #0] + \op w1, [x7, 0] + .endm + + /* , [{,#0}] */ + .macro LR64 op + \op x1, [x7] + \op x1, [x7, #0] + \op x1, [x7, 0] + .endm + +func: + .irp op, ldaprb, ldaprh, ldapr + LR32 \op + .endr + + LR64 ldapr diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index eb1274b..6960a56 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2958,6 +2958,9 @@ struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q), CORE_INSN ("stlr", 0x889ffc00, 0xbfe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), CORE_INSN ("ldar", 0x88dffc00, 0xbfeffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), + V8_3_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), + V8_3_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), + V8_3_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), /* Limited Ordering Regions load/store instructions. */ _LOR_INSN ("ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), _LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),