| Message ID | 20240709-add_qcs9100_llcc_compatible-v2-1-99d203616eed@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | soc: qcom: llcc: Add QCS9100 LLCC compatible | expand |
diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index 68ea5f70b75f..a38c8b99099e 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -21,6 +21,7 @@ properties: compatible: enum: - qcom,qdu1000-llcc + - qcom,qcs9100-llcc - qcom,sa8775p-llcc - qcom,sc7180-llcc - qcom,sc7280-llcc @@ -85,6 +86,7 @@ allOf: compatible: contains: enum: + - qcom,qcs9100-llcc - qcom,sa8775p-llcc then: properties:
Add the cache controller compatible and register region descriptions for QCS9100 platform. QCS9100 is drived from SA8775p. Currently, both the QCS9100 and SA8775p platform use non-SCMI resource. In the future, the SA8775p platform will move to use SCMI resources and it will have new sa8775p-related device tree. Consequently, introduce "qcom,qcs9100-llcc" to describe non-SCMI based LLCC. Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> --- Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 2 ++ 1 file changed, 2 insertions(+)