From patchwork Thu Nov 10 13:52:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 81659 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp740273qge; Thu, 10 Nov 2016 06:04:23 -0800 (PST) X-Received: by 10.55.149.134 with SMTP id x128mr5108327qkd.263.1478786663283; Thu, 10 Nov 2016 06:04:23 -0800 (PST) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id a134si3408136qkb.306.2016.11.10.06.04.22; Thu, 10 Nov 2016 06:04:23 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id E37F660D39; Thu, 10 Nov 2016 14:04:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 0A79060E90; Thu, 10 Nov 2016 13:57:29 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 539EC60844; Thu, 10 Nov 2016 13:57:16 +0000 (UTC) Received: from mail-pf0-f181.google.com (mail-pf0-f181.google.com [209.85.192.181]) by lists.linaro.org (Postfix) with ESMTPS id B135760E48 for ; Thu, 10 Nov 2016 13:53:40 +0000 (UTC) Received: by mail-pf0-f181.google.com with SMTP id i88so146367531pfk.2 for ; Thu, 10 Nov 2016 05:53:40 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FaMQ5XiojL4d02zP7RSUVvoMdgQKojiGDn+ElOnAhUs=; b=mcNlIQYk4FFI9l5lbEtUf4PMq6S4n6TEowzHJFHKsQjHwR68Oz6Z/K/VLdjWfwq+fc X3PtuwmCFDpNYSv6Q/iDMPknA6Ne3U+iMc1TJadECyJ8OHLfAICgi30g3jRCoIENEZi7 tfDA3HxRnAQ1/qCrk2sYJpktjq9PE6BDNtpz+mzYkl4bTGIhGhaJi/huQaje8kMrYD0+ NU2ywEPKuCH/8GisLfDODKMPqTNjG2Imo0cqeC4Xd/TZGpUFSEe9XgANy0tnfkX1jI1U xvhxMugcoSX9ZbyQyqnumCzs+4nkd0+GuZKP9krKo3eXqcyWtdtsTMB6lZRHmpPQ+L6j Q2vg== X-Gm-Message-State: ABUngvcGkmUvLkkjEmeXiGAzDP2SjzpYDHz/7lQFUj7ACVH0iTYa7zv8nh4APBQatiL98cYq3Qs= X-Received: by 10.99.44.84 with SMTP id s81mr35991253pgs.153.1478786020056; Thu, 10 Nov 2016 05:53:40 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g78sm7625705pfe.19.2016.11.10.05.53.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 Nov 2016 05:53:39 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Thu, 10 Nov 2016 21:52:13 +0800 Message-Id: <1478785950-24197-10-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1478785950-24197-1-git-send-email-heyi.guo@linaro.org> References: <1478785950-24197-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [PATCH 09/27] Hisilicon/HwMemInitLib.h: fix typo for phyDqsFallRiseDelay X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" phyDqsFallRiseDelay was spelt as phyDqs*Fail*RiseDelay; just fix the typo. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo --- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index f424ae9..8968b21 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -228,7 +228,7 @@ typedef struct _DDR_Channel{ UINT8 per_cs_training_en; UINT32 phyRdDataEnIeDly; UINT32 phyPadCalConfig; - UINT32 phyDqsFailRiseDelay; + UINT32 phyDqsFallRiseDelay; UINT32 ddrcCfgDfiLat0; UINT32 ddrcCfgDfiLat1; UINT32 parityLatency;