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[209.132.180.131]) by mx.google.com with ESMTPS id m26si2659799pfg.240.2016.11.17.02.22.50 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Nov 2016 02:22:50 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-return-94484-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org; spf=pass (google.com: domain of binutils-return-94484-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=binutils-return-94484-patch=linaro.org@sourceware.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:to:cc:from:subject:message-id:date :mime-version:content-type; q=dns; s=default; b=jVYoQKFhnrjbQ7Rs uLgeWtg6eZLZkRy7BeGcUKvic0swWjVxT4leVP8pHJDJoYetgEkMgK95aV4lrNV0 bpQapI7S9l8yqoAjh7pk0bVgvm1vfMCb5IaZqSP+IjoyXPY3QCHm7cimNwYjlhqQ Fep7rbpdlQSG1bNTBKumFgEbmXM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:to:cc:from:subject:message-id:date :mime-version:content-type; s=default; bh=/mnCv2IPgU16vOY1eSFFKt OhbhM=; b=PwmLyqzTRvPpbCzPXuktq6OqO6j8lZJAWbTCfM69p4fsQLKo4h5FE7 JwvOHHrcblFi5lUFB6XsnP5IBqowQ1UuB7XyCe6Kjg5MRapvmJg9E8OXruXf9ygf pNB9YYcSWt2tShUxIUwEYOv8FJro4IvKuEo+ySzyY26VJHT0aqcXg= Received: (qmail 111743 invoked by alias); 17 Nov 2016 10:22:34 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Delivered-To: mailing list binutils@sourceware.org Received: (qmail 110964 invoked by uid 89); 17 Nov 2016 10:22:32 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.8 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=disassembly, 2016-11-17 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 17 Nov 2016 10:22:22 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 518DCAD7; Thu, 17 Nov 2016 02:22:21 -0800 (PST) Received: from [10.2.207.43] (e104453-lin.cambridge.arm.com [10.2.207.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 669883F318; Thu, 17 Nov 2016 02:22:20 -0800 (PST) To: "binutils@sourceware.org" Cc: Nicholas Clifton , doko@debian.org, Ramana Radhakrishnan , Richard Earnshaw From: Renlin Li Subject: [GAS][ARM][PR20827]Fix gas error for two register form instruction (pre-UAL syntax). Message-ID: <582D84DA.4060108@foss.arm.com> Date: Thu, 17 Nov 2016 10:22:18 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 X-IsSubscribed: yes Hi all, Previously, I had a patch to emit warning for PC used in data processing instructions with register-shifted register operand. https://sourceware.org/ml/binutils/2016-10/msg00073.html It will assert if any operand is not presented before the shifted register operand. However, there is a relaxation of requirements I had missed in pre-UAL syntax. If the destination register is the same as the first operand, a two register form of the instruction can be used. so the following two instruction are the same. 1) add r5, r4, lsl r0 2) add r5, r5, r4, lsl r0 Although, the preferred form for ALU instructions specifies three registers, even if the destination register is the same as the first operand. If unified syntax is selected, gas will give error for instruction 1) during operand parsing. This patch fixes the bug. binutils arm-none-eabi regression test checked Okay. Okay to check in the change? The previous change is not in the 2.27 release branch. So the 2.27 shouldn't have the problem. Regards, Renlin gas/ChangeLog: 2016-11-17 Renlin Li * config/tc-arm.c (encode_arm_shift): Don't assert for operands not presented. * testsuite/gas/arm/add-shift-two.d: New. * testsuite/gas/arm/add-shift-two.s: New. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 9a12bcc..e37d354 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -7435,8 +7435,11 @@ encode_arm_shift (int i) int index; for (index = 0; index <= i; ++index) { - gas_assert (inst.operands[index].present); - if (inst.operands[index].isreg && inst.operands[index].reg == REG_PC) + /* Check the operand only when it's presented. In pre-UAL syntax, + if the destination register is the same as the first operand, two + register form of the instruction can be used. */ + if (inst.operands[index].present && inst.operands[index].isreg + && inst.operands[index].reg == REG_PC) as_warn (UNPRED_REG ("r15")); } diff --git a/gas/testsuite/gas/arm/add-shift-two.d b/gas/testsuite/gas/arm/add-shift-two.d new file mode 100644 index 0000000..46a58c5 --- /dev/null +++ b/gas/testsuite/gas/arm/add-shift-two.d @@ -0,0 +1,11 @@ +# name: Two register form of data processing instruction with register shifted register operand +# as: +# objdump: -dr + +.*: +file format .*arm.* + +Disassembly of section .text: + +00000000 <.text>: + 0: e0855014 add r5, r5, r4, lsl r0 + 4: e0855014 add r5, r5, r4, lsl r0 diff --git a/gas/testsuite/gas/arm/add-shift-two.s b/gas/testsuite/gas/arm/add-shift-two.s new file mode 100644 index 0000000..72560cd --- /dev/null +++ b/gas/testsuite/gas/arm/add-shift-two.s @@ -0,0 +1,5 @@ + .arch armv7-a + .text + # PR 20827 + add r5, r4, lsl r0 + add r5, r5, r4, lsl r0