From patchwork Fri Nov 18 09:23:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 82850 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp1239602qge; Fri, 18 Nov 2016 01:23:48 -0800 (PST) X-Received: by 10.129.156.139 with SMTP id t133mr6398427ywg.83.1479461028078; Fri, 18 Nov 2016 01:23:48 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x143si17123ybg.204.2016.11.18.01.23.47; Fri, 18 Nov 2016 01:23:48 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753184AbcKRJXo (ORCPT + 7 others); Fri, 18 Nov 2016 04:23:44 -0500 Received: from mail-pg0-f53.google.com ([74.125.83.53]:33838 "EHLO mail-pg0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752870AbcKRJXk (ORCPT ); Fri, 18 Nov 2016 04:23:40 -0500 Received: by mail-pg0-f53.google.com with SMTP id x23so98562752pgx.1 for ; Fri, 18 Nov 2016 01:23:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=xBst9EJ6hcpnYwwIH0d/Hw9nm6KqRQXMBmfpaxzyqbw=; b=CNzDk4y9GdBpNujnKsY8CD3FmbUhBw1gurDtnslxqpsUx4bes0soYSeA+cy7ZP1JtU a7lHC7m5x8mcGR5ForDB8jf+k6fU8ZBMkejXcGlmT7AO12ST07PQbJtUwWzZLoCS6n9f 6PQJKFWpGsy9riNdIsKRBkddVIKGxhCYxMSp8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=xBst9EJ6hcpnYwwIH0d/Hw9nm6KqRQXMBmfpaxzyqbw=; b=PzehsEwOv6r8tpixhBYBhH9QqkIJC2EdJ7B+lJbhdsMMXDKwkfXV52Q44MEK2NpogG 140L+gCdkW62Yyfzv3nVraou7YATNuwzFBqrVpjv2VBWA85BSwK2kJjiknEB+wzs9wKI 9uE9GBl2cpHwZ9JW2Drhdb/gnUj1NeHQQ+1rRnxKGCUL4lobyMLESldFCKQGtVplvQMg 39/fc9QNQ1DK89pk+l3Xez1NCQ+bRKqz1WhuxQRo9o6yw9hbF6KIY91OQUXME3Y9vG4r Sac57C+97ZqWJw4UhGdgn2Dh/+hmX5o+RWL9rFFtFIZXmsel21/DBQZ7AiJn7ofVjCyZ +Muw== X-Gm-Message-State: ABUngvcPr3jMGRgtophqmoknGIR94CKuEdQ1P7N4Ku8zay7Ibn5XasvyiBEHaWmf+S+ZreOL X-Received: by 10.99.139.199 with SMTP id j190mr17124845pge.115.1479461018804; Fri, 18 Nov 2016 01:23:38 -0800 (PST) Received: from localhost ([122.172.89.192]) by smtp.gmail.com with ESMTPSA id q26sm15594692pfk.94.2016.11.18.01.23.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 Nov 2016 01:23:38 -0800 (PST) From: Viresh Kumar To: Rafael Wysocki , Viresh Kumar , Nishanth Menon , Stephen Boyd Cc: linaro-kernel@lists.linaro.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Mark Rutland , Kevin Hilman , Ulf Hansson , Vincent Guittot , Lina Iyer , devicetree@vger.kernel.org, Nayak Rajendra , Viresh Kumar Subject: [PATCH 2/2] PM / OPP: Introduce domain-performance-state binding to OPP nodes Date: Fri, 18 Nov 2016 14:53:13 +0530 Message-Id: <76c8ccbb551cd513c32001f3da6986a3356becbd.1479459752.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.7.1.410.g6faf27b In-Reply-To: References: In-Reply-To: References: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some platforms have the capability to configure the performance state of their Power Domains. The performance levels are represented by positive integer values, a lower value represents lower performance state. If the consumers don't need the capability of switching to different domain performance states at runtime, then they can simply define their required domain performance state in their nodes directly. But if the device needs the capability of switching to different domain performance states, as they may need to support different clock rates, then the per OPP node can be used to contain that information. This patch introduces the domain-performance-state (already defined by Power Domain bindings) to the per OPP node. It can contain a single positive integer value. An example is also provided. Signed-off-by: Viresh Kumar --- Documentation/devicetree/bindings/opp/opp.txt | 57 +++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) -- 2.7.1.410.g6faf27b -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt index ee91cbdd95ee..9fb7804f784d 100644 --- a/Documentation/devicetree/bindings/opp/opp.txt +++ b/Documentation/devicetree/bindings/opp/opp.txt @@ -145,6 +145,14 @@ properties. - status: Marks the node enabled/disabled. +- domain-performance-state: A positive integer value representing the minimum + performance level (of the parent domain) required by the consumer for the + working of respective OPP. The integer value '1' represents the lowest + performance level and the highest value represents the highest performance + level. The consumer device node (which contains phandle to the OPP table in + its "operating-points-v2" property) should have its "power-domains" property + set as well. + Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together. / { @@ -517,3 +525,52 @@ Example 5: opp-supported-hw }; }; }; + +Example 7: domain-Performance-state: +(example: For 1GHz require domain state 1 and for 1.1 & 1.2 GHz require state 2) + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + clocks = <&clk_controller 0>; + clock-names = "cpu"; + cpu-supply = <&cpu_supply0>; + operating-points-v2 = <&cpu0_opp_table>; + power-domains = <&foo_pd>; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp@1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <970000 975000 985000>; + opp-microamp = <70000>; + clock-latency-ns = <300000>; + opp-suspend; + domain-performance-state = <1>; + }; + opp@1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <980000 1000000 1010000>; + opp-microamp = <80000>; + clock-latency-ns = <310000>; + domain-performance-state = <2>; + }; + opp@1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1025000>; + clock-latency-ns = <290000>; + turbo-mode; + domain-performance-state = <2>; + }; + }; +};