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[54.225.227.206]) by mx.google.com with ESMTP id c198si7661906qka.31.2016.11.19.00.46.38; Sat, 19 Nov 2016 00:46:39 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id BC2A763501; Sat, 19 Nov 2016 08:46:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id A6D7560CEA; Sat, 19 Nov 2016 08:41:56 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 48AC0634E9; Sat, 19 Nov 2016 08:41:38 +0000 (UTC) Received: from mail-pf0-f182.google.com (mail-pf0-f182.google.com [209.85.192.182]) by lists.linaro.org (Postfix) with ESMTPS id 9CF7260CEA for ; Sat, 19 Nov 2016 08:39:38 +0000 (UTC) Received: by mail-pf0-f182.google.com with SMTP id c4so45954085pfb.1 for ; Sat, 19 Nov 2016 00:39:38 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=70pnxgoz5CQ/ar8uymV3TvauyOMNgsJzxNeAI7eq6Ic=; b=KoIzLRcQg5/IP8NG8yYGlmkSlSxd5bUAbmBSPyvb1eYz1JKjdcVNYlWTN7rBThjFZh +S7AguVwxffxEhyaZFR0Nq4XtiD8HS7lq1cAzRfbfH58TlZJ44vuZFIKXZCZ7g/ApLKG jttvGhB89hT+E4vMyiYPf9F+y893vthVkZGkqBTGQ0XZs4GgPty0ebREw+dSHyUo3D/O M3v4s2nw/hJqnKMkLJLF+AI9wvL2khYOBqwL62HJlreJyEVYE8xlfmFruveJEsRaiFXq LHLdsbqq8yEyohJx9mveUk3ZCNj+cSNIghFSAIYOFvOq9NFSHgV1HskF+nw4M3eJ+3Po GP9w== X-Gm-Message-State: AKaTC00sgxfKsJLLbfROYrorYVbumJTg98xo6PbJBlM7lZklnh1Xei0tvx+HkArdrgrUplkKU9E= X-Received: by 10.99.232.21 with SMTP id s21mr8527898pgh.19.1479544777863; Sat, 19 Nov 2016 00:39:37 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id v193sm5106241pgb.37.2016.11.19.00.39.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 19 Nov 2016 00:39:37 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Sat, 19 Nov 2016 16:37:24 +0800 Message-Id: <1479544691-59575-10-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479544691-59575-1-git-send-email-heyi.guo@linaro.org> References: <1479544691-59575-1-git-send-email-heyi.guo@linaro.org> Cc: Peicong Li Subject: [Linaro-uefi] [Patch v4 09/56] Hisilicon/Serdes: add support for D05 X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Modify OemGetSerdesParam interface to support D05, for it has 2 sockets on the board, and each socket has 2 IO super clusters. The interface is modified to support getting serdes parameter for both IO super clusters (denoted as A and B) on each socket. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Peicong Li Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm --- .../Type09/MiscSystemSlotDesignationFunction.c | 23 ++++++++++------------ Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 2 +- Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h | 2 +- .../D02/Library/OemMiscLibD02/BoardFeatureD02.c | 9 ++++----- .../Library/OemMiscLib2P/BoardFeature2PHi1610.c | 7 +++---- 5 files changed, 19 insertions(+), 24 deletions(-) diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c index a0e3de3..62e4b7f 100644 --- a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c +++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c @@ -73,9 +73,10 @@ UpdateSlotUsage( ) { EFI_STATUS Status; - serdes_param_t sSerdesParam; + serdes_param_t SerdesParamA; + serdes_param_t SerdesParamB; - Status = OemGetSerdesParam (&sSerdesParam); + Status = OemGetSerdesParam (&SerdesParamA, &SerdesParamB, 0); if(EFI_ERROR(Status)) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] OemGetSerdesParam failed %r\n", __FUNCTION__, __LINE__, Status)); @@ -85,8 +86,8 @@ UpdateSlotUsage( // // PCIE0 // - if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data) && sSerdesParam.hilink1_mode == EM_HILINK1_PCIE0_8LANE) - { + if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data) + && SerdesParamA.hilink1_mode == EM_HILINK1_PCIE0_8LANE) { InputData->CurrentUsage = SlotUsageAvailable; } @@ -95,8 +96,7 @@ UpdateSlotUsage( // if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie1Data) { - if (sSerdesParam.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) - { + if (SerdesParamA.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) { InputData->SlotDataBusWidth = SlotDataBusWidth4X; } } @@ -106,13 +106,10 @@ UpdateSlotUsage( // if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie2Data) { - if (sSerdesParam.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) - { + if (SerdesParamA.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) { InputData->SlotDataBusWidth = SlotDataBusWidth4X; InputData->CurrentUsage = SlotUsageAvailable; - } - else if (sSerdesParam.hilink2_mode == EM_HILINK2_PCIE2_8LANE) - { + } else if (SerdesParamA.hilink2_mode == EM_HILINK2_PCIE2_8LANE) { InputData->CurrentUsage = SlotUsageAvailable; } } @@ -120,8 +117,8 @@ UpdateSlotUsage( // // PCIE3 // - if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data) && sSerdesParam.hilink5_mode == EM_HILINK5_PCIE3_4LANE) - { + if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data) + && SerdesParamA.hilink5_mode == EM_HILINK5_PCIE3_4LANE) { InputData->CurrentUsage = SlotUsageAvailable; } } diff --git a/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h index 700d40e..3bd5a0f 100755 --- a/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h +++ b/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h @@ -82,7 +82,7 @@ typedef struct { UINT32 DsCfg; } SERDES_POLARITY_INVERT; -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param); +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; UINT32 GetEthType(UINT8 EthChannel); diff --git a/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h index 070934b..b6c7e20 100644 --- a/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h +++ b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h @@ -76,7 +76,7 @@ typedef struct { } SERDES_POLARITY_INVERT; -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param); +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; UINT32 GetEthType(UINT8 EthChannel); diff --git a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c index d4aa84a..7526644 100644 --- a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c +++ b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c @@ -59,15 +59,14 @@ serdes_param_t gSerdesParam = { .hilink5_mode = EM_HILINK5_SAS1_4LANE, }; -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param) +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId) { - if (NULL == Param) - { - DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__)); + if (ParamA == NULL) { + DEBUG((DEBUG_ERROR, "[%a]:[%dL] ParamA == NULL!\n", __FUNCTION__, __LINE__)); return EFI_INVALID_PARAMETER; } - (VOID) CopyMem(Param, &gSerdesParam, sizeof(*Param)); + (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA)); return EFI_SUCCESS; } diff --git a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c index 23c55e1..a54e76f 100644 --- a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c +++ b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c @@ -75,15 +75,14 @@ serdes_param_t gSerdesParam1 = { .use_ssc = 0, }; -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param) +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId) { - if (NULL == Param) - { + if (ParamA == NULL) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__)); return EFI_INVALID_PARAMETER; } - (VOID) CopyMem(Param, &gSerdesParam, sizeof(*Param)); + (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA)); return EFI_SUCCESS; }