| Message ID | 1479544691-59575-43-git-send-email-heyi.guo@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
Assuming IORT value are correct. Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org> On Sat, Nov 19, 2016 at 04:37:57PM +0800, Heyi Guo wrote: > This patch adds the support of RoCE to the DSDT and IORT > ACPI Tables. Following are the changes: > 1. adds the support of a RoCE device to the HNS DSDT file. > RoCE DEVICE node properties added are: > * eth-handle > * dsaf-handle > * interrupt-parent > * interrupt-names > 2. Interrupt node > 3. Addition of MbiGen RoCE "named-component" node in the > IORT Table. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Salil Mehta <salil.mehta@huawei.com> > --- > .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 33 ++++++++++++- > .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 55 +++++++++++++++++++++- > .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 23 ++++++++- > 3 files changed, 108 insertions(+), 3 deletions(-) > > diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl > index e02b4d5..db98305 100644 > --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl > +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl > @@ -7,7 +7,7 @@ > * Format: [ByteLength] FieldName : HexFieldValue > */ > [0004] Signature : "IORT" [IO Remapping Table] > -[0004] Table Length : 0000029e > +[0004] Table Length : 000002e4 > [0001] Revision : 00 > [0001] Checksum : BC > [0006] Oem ID : "HISI " > @@ -249,6 +249,37 @@ > [0004] Flags (decoded below) : 00000000 > Single Mapping : 1 > > +/* mbi-gen mbi7 - RoCE named component */ > +[0001] Type : 01 > +[0002] Length : 0046 > +[0001] Revision : 00 > +[0004] Reserved : 00000000 > +[0004] Mapping Count : 00000001 > +[0004] Mapping Offset : 00000032 > + > +[0004] Node Flags : 00000000 > +[0008] Memory Properties : [IORT Memory Access Properties] > +[0004] Cache Coherency : 00000000 > +[0001] Hints (decoded below) : 00 > + Transient : 0 > + Write Allocate : 0 > + Read Allocate : 0 > + Override : 0 > +[0002] Reserved : 0000 > +[0001] Memory Flags (decoded below) : 00 > + Coherency : 0 > + Device Attribute : 0 > +[0001] Memory Size Limit : 00 > +[0016] Device Name : "\_SB_.MBI7" > +[0004] Padding : 00 00 00 00 > + > +[0004] Input base : 00000000 > +[0004] ID Count : 00000001 > +[0004] Output Base : 00040b1e > +[0004] Output Reference : 00000034 > +[0004] Flags (decoded below) : 00000000 > + Single Mapping : 1 > + > /* RC 0 */ > [0001] Type : 02 > [0002] Length : 0034 > diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl > index 9a7fdb0..5997910 100644 > --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl > +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl > @@ -558,5 +558,58 @@ Scope(_SB) > } > }) > } > - > + Device (ROCE) { > + Name(_HID, "HISI00D1") > + Name (_CCA, 1) // Cache-coherent controller > + Name (_DSD, Package () { > + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), > + Package () { > + Package () {"eth-handle", Package () {\_SB.ETH0, \_SB.ETH1, 0, 0, \_SB.ETH4, \_SB.ETH5}}, > + Package () {"dsaf-handle", Package (){\_SB.DSF0}}, > + Package () {"interrupt-names", Package() {"hns-roce-comp-0", > + "hns-roce-comp-1", > + "hns-roce-comp-2", > + "hns-roce-comp-3", > + "hns-roce-comp-4", > + "hns-roce-comp-5", > + "hns-roce-comp-6", > + "hns-roce-comp-7", > + "hns-roce-comp-8", > + "hns-roce-comp-9", > + "hns-roce-comp-10", > + "hns-roce-comp-11", > + "hns-roce-comp-12", > + "hns-roce-comp-13", > + "hns-roce-comp-14", > + "hns-roce-comp-15", > + "hns-roce-comp-16", > + "hns-roce-comp-17", > + "hns-roce-comp-18", > + "hns-roce-comp-19", > + "hns-roce-comp-20", > + "hns-roce-comp-21", > + "hns-roce-comp-22", > + "hns-roce-comp-23", > + "hns-roce-comp-24", > + "hns-roce-comp-25", > + "hns-roce-comp-26", > + "hns-roce-comp-27", > + "hns-roce-comp-28", > + "hns-roce-comp-29", > + "hns-roce-comp-30", > + "hns-roce-comp-31", > + "hns-roce-async", > + "hns-roce-common"}}, > + } > + }) > + Name (_CRS, ResourceTemplate (){ > + Memory32Fixed (ReadWrite, 0xc4000000 , 0x100000) > + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI7") > + { > + 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, > + 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, > + 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, > + } > + }) > + } > } > diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl > index 5456bd8..afd6b47 100644 > --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl > +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl > @@ -280,5 +280,26 @@ Name(_PRS, ResourceTemplate() { > } > }) > } > - > + Device(MBI7) { // Mbi-gen roce intc > + Name(_HID, "HISI0152") > + Name(_CID, "MBIGen") > + Name(_CRS, ResourceTemplate() { > + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) > + }) > + Name (_PRS, ResourceTemplate (){ > + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) > + { > + 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, > + 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, > + 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, > + } > + }) > + Name(_DSD, Package () { > + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), > + Package () > + { > + Package () {"num-pins", 34} > + } > + }) > + } > } > -- > 1.9.1 >
On Sat, Nov 19, 2016 at 04:37:57PM +0800, Heyi Guo wrote: > This patch adds the support of RoCE to the DSDT and IORT > ACPI Tables. Following are the changes: > 1. adds the support of a RoCE device to the HNS DSDT file. > RoCE DEVICE node properties added are: > * eth-handle > * dsaf-handle > * interrupt-parent > * interrupt-names > 2. Interrupt node > 3. Addition of MbiGen RoCE "named-component" node in the > IORT Table. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Salil Mehta <salil.mehta@huawei.com> And with Graeme's Reviewed-by: Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> > --- > .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 33 ++++++++++++- > .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 55 +++++++++++++++++++++- > .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 23 ++++++++- > 3 files changed, 108 insertions(+), 3 deletions(-) > > diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl > index e02b4d5..db98305 100644 > --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl > +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl > @@ -7,7 +7,7 @@ > * Format: [ByteLength] FieldName : HexFieldValue > */ > [0004] Signature : "IORT" [IO Remapping Table] > -[0004] Table Length : 0000029e > +[0004] Table Length : 000002e4 > [0001] Revision : 00 > [0001] Checksum : BC > [0006] Oem ID : "HISI " > @@ -249,6 +249,37 @@ > [0004] Flags (decoded below) : 00000000 > Single Mapping : 1 > > +/* mbi-gen mbi7 - RoCE named component */ > +[0001] Type : 01 > +[0002] Length : 0046 > +[0001] Revision : 00 > +[0004] Reserved : 00000000 > +[0004] Mapping Count : 00000001 > +[0004] Mapping Offset : 00000032 > + > +[0004] Node Flags : 00000000 > +[0008] Memory Properties : [IORT Memory Access Properties] > +[0004] Cache Coherency : 00000000 > +[0001] Hints (decoded below) : 00 > + Transient : 0 > + Write Allocate : 0 > + Read Allocate : 0 > + Override : 0 > +[0002] Reserved : 0000 > +[0001] Memory Flags (decoded below) : 00 > + Coherency : 0 > + Device Attribute : 0 > +[0001] Memory Size Limit : 00 > +[0016] Device Name : "\_SB_.MBI7" > +[0004] Padding : 00 00 00 00 > + > +[0004] Input base : 00000000 > +[0004] ID Count : 00000001 > +[0004] Output Base : 00040b1e > +[0004] Output Reference : 00000034 > +[0004] Flags (decoded below) : 00000000 > + Single Mapping : 1 > + > /* RC 0 */ > [0001] Type : 02 > [0002] Length : 0034 > diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl > index 9a7fdb0..5997910 100644 > --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl > +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl > @@ -558,5 +558,58 @@ Scope(_SB) > } > }) > } > - > + Device (ROCE) { > + Name(_HID, "HISI00D1") > + Name (_CCA, 1) // Cache-coherent controller > + Name (_DSD, Package () { > + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), > + Package () { > + Package () {"eth-handle", Package () {\_SB.ETH0, \_SB.ETH1, 0, 0, \_SB.ETH4, \_SB.ETH5}}, > + Package () {"dsaf-handle", Package (){\_SB.DSF0}}, > + Package () {"interrupt-names", Package() {"hns-roce-comp-0", > + "hns-roce-comp-1", > + "hns-roce-comp-2", > + "hns-roce-comp-3", > + "hns-roce-comp-4", > + "hns-roce-comp-5", > + "hns-roce-comp-6", > + "hns-roce-comp-7", > + "hns-roce-comp-8", > + "hns-roce-comp-9", > + "hns-roce-comp-10", > + "hns-roce-comp-11", > + "hns-roce-comp-12", > + "hns-roce-comp-13", > + "hns-roce-comp-14", > + "hns-roce-comp-15", > + "hns-roce-comp-16", > + "hns-roce-comp-17", > + "hns-roce-comp-18", > + "hns-roce-comp-19", > + "hns-roce-comp-20", > + "hns-roce-comp-21", > + "hns-roce-comp-22", > + "hns-roce-comp-23", > + "hns-roce-comp-24", > + "hns-roce-comp-25", > + "hns-roce-comp-26", > + "hns-roce-comp-27", > + "hns-roce-comp-28", > + "hns-roce-comp-29", > + "hns-roce-comp-30", > + "hns-roce-comp-31", > + "hns-roce-async", > + "hns-roce-common"}}, > + } > + }) > + Name (_CRS, ResourceTemplate (){ > + Memory32Fixed (ReadWrite, 0xc4000000 , 0x100000) > + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI7") > + { > + 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, > + 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, > + 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, > + } > + }) > + } > } > diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl > index 5456bd8..afd6b47 100644 > --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl > +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl > @@ -280,5 +280,26 @@ Name(_PRS, ResourceTemplate() { > } > }) > } > - > + Device(MBI7) { // Mbi-gen roce intc > + Name(_HID, "HISI0152") > + Name(_CID, "MBIGen") > + Name(_CRS, ResourceTemplate() { > + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) > + }) > + Name (_PRS, ResourceTemplate (){ > + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) > + { > + 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, > + 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, > + 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, > + } > + }) > + Name(_DSD, Package () { > + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), > + Package () > + { > + Package () {"num-pins", 34} > + } > + }) > + } > } > -- > 1.9.1 >
diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl index e02b4d5..db98305 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl @@ -7,7 +7,7 @@ * Format: [ByteLength] FieldName : HexFieldValue */ [0004] Signature : "IORT" [IO Remapping Table] -[0004] Table Length : 0000029e +[0004] Table Length : 000002e4 [0001] Revision : 00 [0001] Checksum : BC [0006] Oem ID : "HISI " @@ -249,6 +249,37 @@ [0004] Flags (decoded below) : 00000000 Single Mapping : 1 +/* mbi-gen mbi7 - RoCE named component */ +[0001] Type : 01 +[0002] Length : 0046 +[0001] Revision : 00 +[0004] Reserved : 00000000 +[0004] Mapping Count : 00000001 +[0004] Mapping Offset : 00000032 + +[0004] Node Flags : 00000000 +[0008] Memory Properties : [IORT Memory Access Properties] +[0004] Cache Coherency : 00000000 +[0001] Hints (decoded below) : 00 + Transient : 0 + Write Allocate : 0 + Read Allocate : 0 + Override : 0 +[0002] Reserved : 0000 +[0001] Memory Flags (decoded below) : 00 + Coherency : 0 + Device Attribute : 0 +[0001] Memory Size Limit : 00 +[0016] Device Name : "\_SB_.MBI7" +[0004] Padding : 00 00 00 00 + +[0004] Input base : 00000000 +[0004] ID Count : 00000001 +[0004] Output Base : 00040b1e +[0004] Output Reference : 00000034 +[0004] Flags (decoded below) : 00000000 + Single Mapping : 1 + /* RC 0 */ [0001] Type : 02 [0002] Length : 0034 diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl index 9a7fdb0..5997910 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl @@ -558,5 +558,58 @@ Scope(_SB) } }) } - + Device (ROCE) { + Name(_HID, "HISI00D1") + Name (_CCA, 1) // Cache-coherent controller + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () {"eth-handle", Package () {\_SB.ETH0, \_SB.ETH1, 0, 0, \_SB.ETH4, \_SB.ETH5}}, + Package () {"dsaf-handle", Package (){\_SB.DSF0}}, + Package () {"interrupt-names", Package() {"hns-roce-comp-0", + "hns-roce-comp-1", + "hns-roce-comp-2", + "hns-roce-comp-3", + "hns-roce-comp-4", + "hns-roce-comp-5", + "hns-roce-comp-6", + "hns-roce-comp-7", + "hns-roce-comp-8", + "hns-roce-comp-9", + "hns-roce-comp-10", + "hns-roce-comp-11", + "hns-roce-comp-12", + "hns-roce-comp-13", + "hns-roce-comp-14", + "hns-roce-comp-15", + "hns-roce-comp-16", + "hns-roce-comp-17", + "hns-roce-comp-18", + "hns-roce-comp-19", + "hns-roce-comp-20", + "hns-roce-comp-21", + "hns-roce-comp-22", + "hns-roce-comp-23", + "hns-roce-comp-24", + "hns-roce-comp-25", + "hns-roce-comp-26", + "hns-roce-comp-27", + "hns-roce-comp-28", + "hns-roce-comp-29", + "hns-roce-comp-30", + "hns-roce-comp-31", + "hns-roce-async", + "hns-roce-common"}}, + } + }) + Name (_CRS, ResourceTemplate (){ + Memory32Fixed (ReadWrite, 0xc4000000 , 0x100000) + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI7") + { + 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, + 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, + 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, + } + }) + } } diff --git a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl index 5456bd8..afd6b47 100644 --- a/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl +++ b/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl @@ -280,5 +280,26 @@ Name(_PRS, ResourceTemplate() { } }) } - + Device(MBI7) { // Mbi-gen roce intc + Name(_HID, "HISI0152") + Name(_CID, "MBIGen") + Name(_CRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xc0080000, 0x10000) + }) + Name (_PRS, ResourceTemplate (){ + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,) + { + 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, + 734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745, + 746, 747, 748, 749, 750, 751, 752, 753, 785, 754, + } + }) + Name(_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () + { + Package () {"num-pins", 34} + } + }) + } }
This patch adds the support of RoCE to the DSDT and IORT ACPI Tables. Following are the changes: 1. adds the support of a RoCE device to the HNS DSDT file. RoCE DEVICE node properties added are: * eth-handle * dsaf-handle * interrupt-parent * interrupt-names 2. Interrupt node 3. Addition of MbiGen RoCE "named-component" node in the IORT Table. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Salil Mehta <salil.mehta@huawei.com> --- .../Hisilicon/Hi1610/Hi1610AcpiTables/D03Iort.asl | 33 ++++++++++++- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Hns.asl | 55 +++++++++++++++++++++- .../Hi1610/Hi1610AcpiTables/Dsdt/D03Mbig.asl | 23 ++++++++- 3 files changed, 108 insertions(+), 3 deletions(-)