From patchwork Wed May 2 02:12:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob X-Patchwork-Id: 8342 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 9612D23E23 for ; Wed, 2 May 2012 02:12:53 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id 5AC38A18040 for ; Wed, 2 May 2012 02:12:53 +0000 (UTC) Received: by yhpp61 with SMTP id p61so202080yhp.11 for ; Tue, 01 May 2012 19:12:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=/B204de/sfBTaDjXyyhGpOmXlOMiBHcM/EoXayg9zRY=; b=pY0o075H+pN/f1ynMMTn8yFoSM/1CTs0sx1NcDYlicgSbf8c7njwIWHl5PLVDDet5H IRhDjX6CfW9I++PkRi+EgKx7Gn7Ub1ZKjyQ5lDjwXzF3JY2vhKfKVZ7sd96EKVh2hUDx kv/bwh6pqUCFVdLfnp4e7Hrf7eFWxnshdXSz3PK5QYiIdeJgxOWmvh1wwv04CYkRn1FT S+CZ89pgF0NYl1njvnH0VBobadcgNM6DRHc4yxF6q+918aVXJlvJ8OE3kScj0I7FK2V1 401v1X0FTvND1fiBDVVxBuD4chIlGs4HVc36Sl0w2CnE3GGVPNgotWxyu6JPDiAhdNyH AApg== Received: by 10.50.217.230 with SMTP id pb6mr3490226igc.1.1335924772614; Tue, 01 May 2012 19:12:52 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.137.198 with SMTP id x6csp219937ibt; Tue, 1 May 2012 19:12:52 -0700 (PDT) Received: by 10.60.27.170 with SMTP id u10mr37094853oeg.50.1335924772015; Tue, 01 May 2012 19:12:52 -0700 (PDT) Received: from mail-ob0-f178.google.com (mail-ob0-f178.google.com [209.85.214.178]) by mx.google.com with ESMTPS id k10si150659oeb.42.2012.05.01.19.12.51 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 01 May 2012 19:12:52 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.214.178 is neither permitted nor denied by best guess record for domain of rob.lee@linaro.org) client-ip=209.85.214.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.214.178 is neither permitted nor denied by best guess record for domain of rob.lee@linaro.org) smtp.mail=rob.lee@linaro.org Received: by mail-ob0-f178.google.com with SMTP id eq6so356335obc.37 for ; Tue, 01 May 2012 19:12:51 -0700 (PDT) Received: by 10.60.27.98 with SMTP id s2mr36181887oeg.48.1335924771826; Tue, 01 May 2012 19:12:51 -0700 (PDT) Received: from localhost.localdomain ([67.23.168.71]) by mx.google.com with ESMTPS id h2sm472219obn.20.2012.05.01.19.12.48 (version=SSLv3 cipher=OTHER); Tue, 01 May 2012 19:12:51 -0700 (PDT) From: Robert Lee To: kernel@pengutronix.de Cc: shawn.guo@linaro.org, amit.kucheria@linaro.org, daniel.lezcano@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linaro-dev@lists.linaro.org, patches@linaro.org, jj@chaosbits.net Subject: [PATCH v2 2/3] ARM: imx: Add imx5 cpuidle driver Date: Tue, 1 May 2012 21:12:39 -0500 Message-Id: <1335924760-796-3-git-send-email-rob.lee@linaro.org> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1335924760-796-1-git-send-email-rob.lee@linaro.org> References: <1335924760-796-1-git-send-email-rob.lee@linaro.org> X-Gm-Message-State: ALoCoQn6xOnSXz5MPf3wHXU17vtF8PuzQCVxzfX00f146PiByWhe6k9G4WqDtH6lg3AKVThgXXxI Add imx5 cpuidle driver. Signed-off-by: Robert Lee --- arch/arm/mach-imx/mm-imx5.c | 42 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index d6b7e9f..cbd9bad 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c @@ -22,24 +22,59 @@ #include #include #include +#include static struct clk *gpc_dvfs_clk; -static void imx5_idle(void) +static int imx5_idle(void) { + int ret = 0; + /* gpc clock is needed for SRPG */ if (gpc_dvfs_clk == NULL) { gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); if (IS_ERR(gpc_dvfs_clk)) - return; + return -ENODEV; } clk_enable(gpc_dvfs_clk); mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); if (!tzic_enable_wake()) cpu_do_idle(); + else + ret = -EBUSY; clk_disable(gpc_dvfs_clk); + + return ret; +} + +static int imx5_cpuidle_enter(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int idx) +{ + int ret; + + ret = imx5_idle(); + + if (ret < 0) + return ret; + + return idx; } +static struct cpuidle_driver imx5_cpuidle_driver = { + .name = "imx5_cpuidle", + .owner = THIS_MODULE, + .en_core_tk_irqen = 1, + .states[0] = { + .enter = imx5_cpuidle_enter, + .exit_latency = 20, /* max latency at 160MHz */ + .target_residency = 1, + .flags = CPUIDLE_FLAG_TIME_VALID, + .name = "IMX5 SRPG", + .desc = "CPU state retained,powered off", + }, + .state_count = 1, +}; + /* * Define the MX50 memory map. */ @@ -103,7 +138,7 @@ void __init imx51_init_early(void) mxc_set_cpu_type(MXC_CPU_MX51); mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); - arm_pm_idle = imx5_idle; + arm_pm_idle = (void *)imx5_idle; } void __init imx53_init_early(void) @@ -238,4 +273,5 @@ void __init imx53_soc_init(void) void __init imx51_init_late(void) { mx51_neon_fixup(); + imx_cpuidle_init(&imx5_cpuidle_driver); }