| Message ID | 20241009161715.14994-1-johan+linaro@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] arm64: dts: qcom: x1e80100: enable GICv3 ITS for PCIe | expand |
On Wed, 09 Oct 2024 18:17:15 +0200, Johan Hovold wrote: > The DWC PCIe controller can be used with its internal MSI controller or > with an external one such as the GICv3 Interrupt Translation Service > (ITS). > > Add the msi-map properties needed to use the GIC ITS. This will also > make Linux switch to the ITS implementation, which allows for assigning > affinity to individual MSIs. This specifically allows NVMe and Wi-Fi > interrupts to be processed on all cores (and not just on CPU0). > > [...] Applied, thanks! [1/1] arm64: dts: qcom: x1e80100: enable GICv3 ITS for PCIe commit: 9c4cd0aef259d41355f90e0dbb2d3574f3830de9 Best regards,
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 1743fe229ded..4d978fe936e5 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2934,6 +2934,8 @@ pcie6a: pci@1bf8000 { linux,pci-domain = <6>; num-lanes = <4>; + msi-map = <0x0 &gic_its 0xe0000 0x10000>; + interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, @@ -3183,6 +3185,8 @@ pcie4: pci@1c08000 { linux,pci-domain = <4>; num-lanes = <2>; + msi-map = <0x0 &gic_its 0xc0000 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, @@ -5773,8 +5777,6 @@ gic_its: msi-controller@17040000 { msi-controller; #msi-cells = <1>; - - status = "disabled"; }; };
The DWC PCIe controller can be used with its internal MSI controller or with an external one such as the GICv3 Interrupt Translation Service (ITS). Add the msi-map properties needed to use the GIC ITS. This will also make Linux switch to the ITS implementation, which allows for assigning affinity to individual MSIs. This specifically allows NVMe and Wi-Fi interrupts to be processed on all cores (and not just on CPU0). Note that using the GIC ITS on x1e80100 will cause Advanced Error Reporting (AER) interrupts to be received on errors unlike when using the internal MSI controller. Consequently, notifications about (correctable) errors may now be logged for errors that previously went unnoticed. Also note that PCIe5 (and PCIe3) can currently only be used with the internal MSI controller due to a platform (firmware) limitation. Signed-off-by: Johan Hovold <johan+linaro@kernel.org> --- The PCIe Gen4 stability fixes [1] are now in 6.12-rc1 so that we can enable the GIC ITS without being flooded with link error notifications [2]. Johan [1] https://lore.kernel.org/lkml/20240911-pci-qcom-gen4-stability-v7-0-743f5c1fd027@linaro.org/ [2] https://lore.kernel.org/lkml/ZpDnSL8as7km9_0b@hovoldconsulting.com/ Changes in v2 - amend commit message with comment about PCIe3 and PCIe5 only supporting the internal MSI controller arch/arm64/boot/dts/qcom/x1e80100.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)