@@ -463,7 +463,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
bg_alpha_enable = true;
- for (i = 0; i < PIPES_PER_STAGE; i++) {
+ for (i = 0; i < PIPES_PER_LM_PAIR; i++) {
if (!pstate->pipe[i].sspp)
continue;
set_bit(pstate->pipe[i].sspp->idx, fetch_active);
@@ -493,7 +493,7 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
if (test_bit(DPU_MIXER_SOURCESPLIT,
&ctx->mixer_hw_caps->features))
- pipes_per_stage = PIPES_PER_STAGE;
+ pipes_per_stage = PIPES_PER_LM_PAIR;
else
pipes_per_stage = 1;
@@ -28,9 +28,9 @@ struct dpu_hw_ctl;
* @multirect_index: index of the rectangle of SSPP.
*/
struct dpu_hw_stage_cfg {
- enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE];
+ enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_LM_PAIR];
enum dpu_sspp_multirect_index multirect_index
- [DPU_STAGE_MAX][PIPES_PER_STAGE];
+ [DPU_STAGE_MAX][PIPES_PER_LM_PAIR];
};
/**
@@ -32,7 +32,8 @@
#define DPU_MAX_PLANES 4
#endif
-#define PIPES_PER_STAGE 2
+#define PIPES_PER_PLANE 2
+#define PIPES_PER_LM_PAIR 2
#ifndef DPU_MAX_DE_CURVES
#define DPU_MAX_DE_CURVES 3
#endif
@@ -633,7 +633,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
return;
/* update sspp */
- for (i = 0; i < PIPES_PER_STAGE; i++) {
+ for (i = 0; i < PIPES_PER_PLANE; i++) {
if (pstate->pipe[i].sspp)
_dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i],
&pstate->pipe_cfg[i].dst_rect,
@@ -1075,7 +1075,7 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane,
* resources are freed by dpu_crtc_assign_plane_resources(),
* but clean them here.
*/
- for (i = 0; i < PIPES_PER_STAGE; i++)
+ for (i = 0; i < PIPES_PER_PLANE; i++)
pstate->pipe[i].sspp = NULL;
return 0;
@@ -1128,7 +1128,7 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
pipe_cfg = &pstate->pipe_cfg[0];
r_pipe_cfg = &pstate->pipe_cfg[1];
- for (i = 0; i < PIPES_PER_STAGE; i++)
+ for (i = 0; i < PIPES_PER_PLANE; i++)
pstate->pipe[i].sspp = NULL;
if (!plane_state->fb)
@@ -1256,7 +1256,7 @@ void dpu_plane_flush(struct drm_plane *plane)
/* force 100% alpha */
_dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
else {
- for (i = 0; i < PIPES_PER_STAGE; i++)
+ for (i = 0; i < PIPES_PER_PLANE; i++)
dpu_plane_flush_csc(pdpu, &pstate->pipe[i]);
}
@@ -1386,7 +1386,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
&fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt));
/* move the assignment here, to ease handling to another pairs later */
- for (i = 0; i < PIPES_PER_STAGE; i++) {
+ for (i = 0; i < PIPES_PER_PLANE; i++) {
if (!pstate->pipe[i].sspp)
continue;
dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i],
@@ -1400,7 +1400,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
pstate->plane_fetch_bw = 0;
pstate->plane_clk = 0;
- for (i = 0; i < PIPES_PER_STAGE; i++) {
+ for (i = 0; i < PIPES_PER_PLANE; i++) {
if (!pstate->pipe[i].sspp)
continue;
pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt,
@@ -1419,7 +1419,7 @@ static void _dpu_plane_atomic_disable(struct drm_plane *plane)
struct dpu_sw_pipe *pipe;
int i;
- for (i = 0; i < PIPES_PER_STAGE; i += 1) {
+ for (i = 0; i < PIPES_PER_PLANE; i += 1) {
pipe = &pstate->pipe[i];
if (!pipe->sspp)
continue;
@@ -1534,7 +1534,7 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p,
drm_printf(p, "\tstage=%d\n", pstate->stage);
- for (i = 0; i < PIPES_PER_STAGE; i++) {
+ for (i = 0; i < PIPES_PER_PLANE; i++) {
pipe = &pstate->pipe[i];
if (!pipe->sspp)
continue;
@@ -1591,7 +1591,7 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
return;
pm_runtime_get_sync(&dpu_kms->pdev->dev);
- for (i = 0; i < PIPES_PER_STAGE; i++) {
+ for (i = 0; i < PIPES_PER_PLANE; i++) {
if (pstate->pipe[i].sspp)
_dpu_plane_set_qos_ctrl(plane, &pstate->pipe[i], enable);
}
@@ -32,8 +32,8 @@
struct dpu_plane_state {
struct drm_plane_state base;
struct msm_gem_address_space *aspace;
- struct dpu_sw_pipe pipe[PIPES_PER_STAGE];
- struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_STAGE];
+ struct dpu_sw_pipe pipe[PIPES_PER_PLANE];
+ struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_PLANE];
enum dpu_stage stage;
bool needs_qos_remap;
bool pending;
Split PIPES_PER_STAGE definition per plane and mixer pair. Because there are more than 2 pipes in quad pipe case, while 2 pipes at most per mixer pair. Signed-off-by: Jun Nie <jun.nie@linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 +++++++++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 ++-- 6 files changed, 17 insertions(+), 16 deletions(-)