[4/6,V2] Exynos5: Add power Enable/Disable for USB-EHCI

Message ID 1336129923-2656-5-git-send-email-rajeshwari.s@samsung.com
State New
Headers show

Commit Message

Rajeshwari Shinde May 4, 2012, 11:12 a.m.
This patch adds functions to enable/disable the power of USB
host controller for EXYNOS5.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
This patchset is based on:
USB: EXYNOS: Add ehci support.patch

 arch/arm/cpu/armv7/exynos/power.c        |   37 ++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-exynos/power.h |    4 +++
 drivers/usb/host/ehci-exynos.c           |    4 +++
 3 files changed, 45 insertions(+), 0 deletions(-)

Comments

Minkyu Kang May 8, 2012, 2:17 a.m. | #1
Dear Rajeshwari Shinde,

On 4 May 2012 20:12, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote:
> This patch adds functions to enable/disable the power of USB
> host controller for EXYNOS5.
>
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> ---

change log.

> This patchset is based on:
> USB: EXYNOS: Add ehci support.patch
>
>  arch/arm/cpu/armv7/exynos/power.c        |   37 ++++++++++++++++++++++++++++++
>  arch/arm/include/asm/arch-exynos/power.h |    4 +++
>  drivers/usb/host/ehci-exynos.c           |    4 +++
>  3 files changed, 45 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
> index c765304..b2944b5 100644
> --- a/arch/arm/cpu/armv7/exynos/power.c
> +++ b/arch/arm/cpu/armv7/exynos/power.c
> @@ -52,3 +52,40 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
>        if (cpu_is_exynos4())
>                exynos4_mipi_phy_control(dev_index, enable);
>  }
> +
> +void exynos5_ps_hold_setup(void)
> +{
> +       struct exynos5_power *power =
> +               (struct exynos5_power *)samsung_get_base_power();
> +
> +       /* Set PS-Hold high */
> +       setbits_le32(&power->ps_hold_control, POWER_PS_HOLD_CONTROL_DATA_HIGH);

Then, we can't set ps_hold to low?

> +}
> +
> +void exynos5_enable_usb_phy(unsigned int enable)
> +{
> +       struct exynos5_power *power =
> +               (struct exynos5_power *)samsung_get_base_power();
> +
> +       if (enable) {
> +               /* Enabling USBHOST_PHY */
> +               setbits_le32(&power->usbhost_phy_control,
> +                               POWER_USB_HOST_PHY_CTRL_EN);
> +       } else {
> +               /* Disabling USBHost_PHY */

USBHOST or USBHost?

> +               clrbits_le32(&power->usbhost_phy_control,
> +                               POWER_USB_HOST_PHY_CTRL_EN);
> +       }
> +}
> +
> +void ps_hold_setup(void)

set_ps_hold_ctrl.

> +{
> +       if (cpu_is_exynos5())
> +               exynos5_ps_hold_setup();
> +}
> +
> +void power_enable_usb_phy(unsigned int enable)

set_usbhost_phy_ctrl.

> +{
> +       if (cpu_is_exynos5())
> +               exynos5_enable_usb_phy(enable);
> +}

Thanks.
Minkyu Kang.
Rajeshwari Birje May 8, 2012, 9:59 a.m. | #2
Hi Minkyu Kang ,

Thank you for the comments.

On Tue, May 8, 2012 at 7:47 AM, Minkyu Kang <promsoft@gmail.com> wrote:
> Dear Rajeshwari Shinde,
>
> On 4 May 2012 20:12, Rajeshwari Shinde <rajeshwari.s@samsung.com> wrote:
>> This patch adds functions to enable/disable the power of USB
>> host controller for EXYNOS5.
>>
>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>> ---
>
> change log.
will do so
>
>> This patchset is based on:
>> USB: EXYNOS: Add ehci support.patch
>>
>>  arch/arm/cpu/armv7/exynos/power.c        |   37 ++++++++++++++++++++++++++++++
>>  arch/arm/include/asm/arch-exynos/power.h |    4 +++
>>  drivers/usb/host/ehci-exynos.c           |    4 +++
>>  3 files changed, 45 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
>> index c765304..b2944b5 100644
>> --- a/arch/arm/cpu/armv7/exynos/power.c
>> +++ b/arch/arm/cpu/armv7/exynos/power.c
>> @@ -52,3 +52,40 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
>>        if (cpu_is_exynos4())
>>                exynos4_mipi_phy_control(dev_index, enable);
>>  }
>> +
>> +void exynos5_ps_hold_setup(void)
>> +{
>> +       struct exynos5_power *power =
>> +               (struct exynos5_power *)samsung_get_base_power();
>> +
>> +       /* Set PS-Hold high */
>> +       setbits_le32(&power->ps_hold_control, POWER_PS_HOLD_CONTROL_DATA_HIGH);
>
> Then, we can't set ps_hold to low?
-- I have removed this function as it is required for PMIC. This pin
need to go high during the booting of our board. Will resubmit this
function when Iam sending patches for PMIC
>
>> +}
>> +
>> +void exynos5_enable_usb_phy(unsigned int enable)
>> +{
>> +       struct exynos5_power *power =
>> +               (struct exynos5_power *)samsung_get_base_power();
>> +
>> +       if (enable) {
>> +               /* Enabling USBHOST_PHY */
>> +               setbits_le32(&power->usbhost_phy_control,
>> +                               POWER_USB_HOST_PHY_CTRL_EN);
>> +       } else {
>> +               /* Disabling USBHost_PHY */
>
> USBHOST or USBHost?
-- Corrected
>
>> +               clrbits_le32(&power->usbhost_phy_control,
>> +                               POWER_USB_HOST_PHY_CTRL_EN);
>> +       }
>> +}
>> +
>> +void ps_hold_setup(void)
>
> set_ps_hold_ctrl.
-- corrected
>
>> +{
>> +       if (cpu_is_exynos5())
>> +               exynos5_ps_hold_setup();
>> +}
>> +
>> +void power_enable_usb_phy(unsigned int enable)
>
> set_usbhost_phy_ctrl.
-- corrected
>
>> +{
>> +       if (cpu_is_exynos5())
>> +               exynos5_enable_usb_phy(enable);
>> +}
>
> Thanks.
> Minkyu Kang.
> --
> from. prom.
> www.promsoft.net
> _______________________________________________
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

Patch

diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c
index c765304..b2944b5 100644
--- a/arch/arm/cpu/armv7/exynos/power.c
+++ b/arch/arm/cpu/armv7/exynos/power.c
@@ -52,3 +52,40 @@  void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
 	if (cpu_is_exynos4())
 		exynos4_mipi_phy_control(dev_index, enable);
 }
+
+void exynos5_ps_hold_setup(void)
+{
+	struct exynos5_power *power =
+		(struct exynos5_power *)samsung_get_base_power();
+
+	/* Set PS-Hold high */
+	setbits_le32(&power->ps_hold_control, POWER_PS_HOLD_CONTROL_DATA_HIGH);
+}
+
+void exynos5_enable_usb_phy(unsigned int enable)
+{
+	struct exynos5_power *power =
+		(struct exynos5_power *)samsung_get_base_power();
+
+	if (enable) {
+		/* Enabling USBHOST_PHY */
+		setbits_le32(&power->usbhost_phy_control,
+				POWER_USB_HOST_PHY_CTRL_EN);
+	} else {
+		/* Disabling USBHost_PHY */
+		clrbits_le32(&power->usbhost_phy_control,
+				POWER_USB_HOST_PHY_CTRL_EN);
+	}
+}
+
+void ps_hold_setup(void)
+{
+	if (cpu_is_exynos5())
+		exynos5_ps_hold_setup();
+}
+
+void power_enable_usb_phy(unsigned int enable)
+{
+	if (cpu_is_exynos5())
+		exynos5_enable_usb_phy(enable);
+}
diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h
index 4236beb..fc44d86 100644
--- a/arch/arm/include/asm/arch-exynos/power.h
+++ b/arch/arm/include/asm/arch-exynos/power.h
@@ -855,4 +855,8 @@  void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable);
 #define EXYNOS_MIPI_PHY_SRESETN		(1 << 1)
 #define EXYNOS_MIPI_PHY_MRESETN		(1 << 2)
 
+void power_enable_usb_phy(unsigned int enable);
+
+#define POWER_USB_HOST_PHY_CTRL_EN		(1 << 0)
+#define POWER_PS_HOLD_CONTROL_DATA_HIGH		(1 << 8)
 #endif
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
index d918a2a..7c7489c 100644
--- a/drivers/usb/host/ehci-exynos.c
+++ b/drivers/usb/host/ehci-exynos.c
@@ -33,6 +33,8 @@  static void setup_usb_phy(struct exynos_usb_phy *usb)
 {
 	enable_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
 
+	power_enable_usb_phy(1);
+
 	clrbits_le32(&usb->usbphyctrl0,
 			HOST_CTRL0_FSEL_MASK |
 			HOST_CTRL0_COMMONON_N |
@@ -73,6 +75,8 @@  static void reset_usb_phy(struct exynos_usb_phy *usb)
 			HOST_CTRL0_SIDDQ |
 			HOST_CTRL0_FORCESUSPEND |
 			HOST_CTRL0_FORCESLEEP);
+
+	power_enable_usb_phy(0);
 }
 
 /*