diff mbox series

[v2,40/54] target/microblaze: Convert to TCGCPUOps.tlb_fill_align

Message ID 20241114160131.48616-41-richard.henderson@linaro.org
State New
Headers show
Series accel/tcg: Convert victim tlb to IntervalTree | expand

Commit Message

Richard Henderson Nov. 14, 2024, 4:01 p.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/cpu.h    |  7 +++----
 target/microblaze/cpu.c    |  2 +-
 target/microblaze/helper.c | 33 ++++++++++++++++++++-------------
 3 files changed, 24 insertions(+), 18 deletions(-)

Comments

Pierrick Bouvier Nov. 14, 2024, 6:53 p.m. UTC | #1 
On 11/14/24 08:01, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/microblaze/cpu.h    |  7 +++----
>   target/microblaze/cpu.c    |  2 +-
>   target/microblaze/helper.c | 33 ++++++++++++++++++++-------------
>   3 files changed, 24 insertions(+), 18 deletions(-)
> 
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 3e5a3e5c60..b0eadfd9b1 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -421,10 +421,9 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc,
>   }
>   
>   #if !defined(CONFIG_USER_ONLY)
> -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> -                     MMUAccessType access_type, int mmu_idx,
> -                     bool probe, uintptr_t retaddr);
> -
> +bool mb_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr address,
> +                            MMUAccessType access_type, int mmu_idx,
> +                           MemOp memop, int size, bool probe, uintptr_t ra);
>   void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
>                                  unsigned size, MMUAccessType access_type,
>                                  int mmu_idx, MemTxAttrs attrs,
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 710eb1146c..212cad2143 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -425,7 +425,7 @@ static const TCGCPUOps mb_tcg_ops = {
>       .restore_state_to_opc = mb_restore_state_to_opc,
>   
>   #ifndef CONFIG_USER_ONLY
> -    .tlb_fill = mb_cpu_tlb_fill,
> +    .tlb_fill_align = mb_cpu_tlb_fill_align,
>       .cpu_exec_interrupt = mb_cpu_exec_interrupt,
>       .cpu_exec_halt = mb_cpu_has_work,
>       .do_interrupt = mb_cpu_do_interrupt,
> diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
> index 5d3259ce31..b6375564b4 100644
> --- a/target/microblaze/helper.c
> +++ b/target/microblaze/helper.c
> @@ -36,37 +36,44 @@ static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu,
>       }
>   }
>   
> -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> -                     MMUAccessType access_type, int mmu_idx,
> -                     bool probe, uintptr_t retaddr)
> +bool mb_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr address,
> +                           MMUAccessType access_type, int mmu_idx,
> +                           MemOp memop, int size,
> +                           bool probe, uintptr_t retaddr)
>   {
>       MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
>       CPUMBState *env = &cpu->env;
>       MicroBlazeMMULookup lu;
>       unsigned int hit;
> -    int prot;
> -    MemTxAttrs attrs = {};
>   
> -    attrs.secure = mb_cpu_access_is_secure(cpu, access_type);
> +    if (address & ((1 << memop_alignment_bits(memop)) - 1)) {
> +        if (probe) {
> +            return false;
> +        }
> +        mb_cpu_do_unaligned_access(cs, address, access_type, mmu_idx, retaddr);
> +    }
> +
> +    memset(out, 0, sizeof(*out));
> +    out->attrs.secure = mb_cpu_access_is_secure(cpu, access_type);
> +    out->lg_page_size = TARGET_PAGE_BITS;
>   
>       if (mmu_idx == MMU_NOMMU_IDX) {
>           /* MMU disabled or not available.  */
> -        address &= TARGET_PAGE_MASK;
> -        prot = PAGE_RWX;
> -        tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx,
> -                                TARGET_PAGE_SIZE);
> +        out->phys_addr = address;
> +        out->prot = PAGE_RWX;
>           return true;
>       }
>   
>       hit = mmu_translate(cpu, &lu, address, access_type, mmu_idx);
>       if (likely(hit)) {
> -        uint32_t vaddr = address & TARGET_PAGE_MASK;
> +        uint32_t vaddr = address;
>           uint32_t paddr = lu.paddr + vaddr - lu.vaddr;
>   
>           qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n",
>                         mmu_idx, vaddr, paddr, lu.prot);
> -        tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, mmu_idx,
> -                                TARGET_PAGE_SIZE);
> +
> +        out->phys_addr = paddr;
> +        out->prot = lu.prot;
>           return true;
>       }
>   

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
diff mbox series

Patch

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 3e5a3e5c60..b0eadfd9b1 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -421,10 +421,9 @@  static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc,
 }
 
 #if !defined(CONFIG_USER_ONLY)
-bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-                     MMUAccessType access_type, int mmu_idx,
-                     bool probe, uintptr_t retaddr);
-
+bool mb_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr address,
+                            MMUAccessType access_type, int mmu_idx,
+                           MemOp memop, int size, bool probe, uintptr_t ra);
 void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
                                unsigned size, MMUAccessType access_type,
                                int mmu_idx, MemTxAttrs attrs,
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 710eb1146c..212cad2143 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -425,7 +425,7 @@  static const TCGCPUOps mb_tcg_ops = {
     .restore_state_to_opc = mb_restore_state_to_opc,
 
 #ifndef CONFIG_USER_ONLY
-    .tlb_fill = mb_cpu_tlb_fill,
+    .tlb_fill_align = mb_cpu_tlb_fill_align,
     .cpu_exec_interrupt = mb_cpu_exec_interrupt,
     .cpu_exec_halt = mb_cpu_has_work,
     .do_interrupt = mb_cpu_do_interrupt,
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 5d3259ce31..b6375564b4 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -36,37 +36,44 @@  static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu,
     }
 }
 
-bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
-                     MMUAccessType access_type, int mmu_idx,
-                     bool probe, uintptr_t retaddr)
+bool mb_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntryFull *out, vaddr address,
+                           MMUAccessType access_type, int mmu_idx,
+                           MemOp memop, int size,
+                           bool probe, uintptr_t retaddr)
 {
     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
     CPUMBState *env = &cpu->env;
     MicroBlazeMMULookup lu;
     unsigned int hit;
-    int prot;
-    MemTxAttrs attrs = {};
 
-    attrs.secure = mb_cpu_access_is_secure(cpu, access_type);
+    if (address & ((1 << memop_alignment_bits(memop)) - 1)) {
+        if (probe) {
+            return false;
+        }
+        mb_cpu_do_unaligned_access(cs, address, access_type, mmu_idx, retaddr);
+    }
+
+    memset(out, 0, sizeof(*out));
+    out->attrs.secure = mb_cpu_access_is_secure(cpu, access_type);
+    out->lg_page_size = TARGET_PAGE_BITS;
 
     if (mmu_idx == MMU_NOMMU_IDX) {
         /* MMU disabled or not available.  */
-        address &= TARGET_PAGE_MASK;
-        prot = PAGE_RWX;
-        tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx,
-                                TARGET_PAGE_SIZE);
+        out->phys_addr = address;
+        out->prot = PAGE_RWX;
         return true;
     }
 
     hit = mmu_translate(cpu, &lu, address, access_type, mmu_idx);
     if (likely(hit)) {
-        uint32_t vaddr = address & TARGET_PAGE_MASK;
+        uint32_t vaddr = address;
         uint32_t paddr = lu.paddr + vaddr - lu.vaddr;
 
         qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n",
                       mmu_idx, vaddr, paddr, lu.prot);
-        tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, mmu_idx,
-                                TARGET_PAGE_SIZE);
+
+        out->phys_addr = paddr;
+        out->prot = lu.prot;
         return true;
     }