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[207.126.144.135]) by mx.google.com with SMTP id m55si6078184eeh.140.2012.05.08.05.18.28 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 08 May 2012 05:18:34 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.135 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.135; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.135 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob113.postini.com ([207.126.147.11]) with SMTP ID DSNKT6kPC2WxqK9cwNh8wPee6AKRCsCh5s3f@postini.com; Tue, 08 May 2012 12:18:34 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 21BEB3D; Tue, 8 May 2012 12:17:47 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id 08B6758; Tue, 8 May 2012 09:57:01 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id A95D224C2E7; Tue, 8 May 2012 14:17:57 +0200 (CEST) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 8 May 2012 14:18:03 +0200 From: Linus Walleij To: Thomas Gleixner , Russell King , Cc: Colin Cross , Rob Herring , Santosh Shilimkar , Shiraz Hashim , Linus Walleij Subject: [PATCH 2/2] ARM: smp_twd: use the .update_freq() for periodic mode Date: Tue, 8 May 2012 14:18:01 +0200 Message-ID: <1336479481-9281-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.9.2 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQlO0batFbmdukz2BO8vYaQQhjEpHuYZvjL5q9Dhk2q0L5ocdqBP0PYBhZ6XkdeOZw23Z3qa From: Linus Walleij When the SMP TWD timer is in periodic mode, the frequency update function will need to call into the driver to update the periodic latch value. Cc: Thomas Gleixner Reported-by: Shiraz Hashim Signed-off-by: Linus Walleij --- arch/arm/kernel/smp_twd.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index fef42b2..7bb2e31 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c @@ -74,6 +74,23 @@ static int twd_set_next_event(unsigned long evt, return 0; } +static void twd_update_freq(enum clock_event_mode mode, + struct clock_event_device *clk) +{ + /* + * The only thing we need to handle here is for the periodic mode, + * where the loaded value needs to be reprogrammed so the new + * frequency is used for the next event. + */ + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + __raw_writel(twd_timer_rate / HZ, twd_base + TWD_TIMER_LOAD); + break; + default: + break; + } +} + /* * local_timer_ack: checks for a local timer interrupt. * @@ -245,6 +262,7 @@ static int __cpuinit twd_timer_setup(struct clock_event_device *clk) clk->rating = 350; clk->set_mode = twd_set_mode; clk->set_next_event = twd_set_next_event; + clk->update_freq = twd_update_freq; clk->irq = twd_ppi; this_cpu_clk = __this_cpu_ptr(twd_evt);