[v4,5/9] net: gmac_rk3288: Add RK3288 GMAC driver

Message ID 1480741572-13582-6-git-send-email-sjg@chromium.org
State New
Headers show

Commit Message

Simon Glass Dec. 3, 2016, 5:06 a.m.
From: Sjoerd Simons <sjoerd.simons@collabora.co.uk>


Add a new driver for the GMAC ethernet interface present in Rockchip
RK3288 SOCs. This driver subclasses the generic design-ware driver to
add the glue needed specifically for Rockchip.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>

Signed-off-by: Simon Glass <sjg@chromium.org>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>

---

Changes in v4: None
Changes in v3:
- Add comments for struct gmac_rk3288_platdata
- Adjust binding to use r/tx-delay instead of r/tx_delay
- Sort includes
- Use debug() instead of printf() for error
- Use function calls instead of fix_mac_speed() hook
- Use new clk interface

Changes in v2:
- Adjust to new hook name
- Fix various coding style nits

 drivers/net/Kconfig       |   7 +++
 drivers/net/Makefile      |   1 +
 drivers/net/gmac_rk3288.c | 154 ++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 162 insertions(+)
 create mode 100644 drivers/net/gmac_rk3288.c

-- 
2.8.0.rc3.226.g39d4020

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Comments

David.Wu Dec. 21, 2016, 2:55 p.m. | #1
Hi Simon,

Could you rename this driver file from rk3288 to rockchip,
and the name of some common function?
The other rockchip socs would use this driver as rk1108, etc.

在 2016/12/3 13:06, Simon Glass 写道:
> From: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
>
> Add a new driver for the GMAC ethernet interface present in Rockchip
> RK3288 SOCs. This driver subclasses the generic design-ware driver to
> add the glue needed specifically for Rockchip.
>
> Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
> ---
>
> Changes in v4: None
> Changes in v3:
> - Add comments for struct gmac_rk3288_platdata
> - Adjust binding to use r/tx-delay instead of r/tx_delay
> - Sort includes
> - Use debug() instead of printf() for error
> - Use function calls instead of fix_mac_speed() hook
> - Use new clk interface
>
> Changes in v2:
> - Adjust to new hook name
> - Fix various coding style nits
>
>   drivers/net/Kconfig       |   7 +++
>   drivers/net/Makefile      |   1 +
>   drivers/net/gmac_rk3288.c | 154 ++++++++++++++++++++++++++++++++++++++++++++++
>   3 files changed, 162 insertions(+)
>   create mode 100644 drivers/net/gmac_rk3288.c
>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index f25d3ff..0027a2e 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -215,4 +215,11 @@ config PIC32_ETH
>   	  This driver implements 10/100 Mbps Ethernet and MAC layer for
>   	  Microchip PIC32 microcontrollers.
>   
> +config GMAC_RK3288
> +	bool "Rockchip RK3288 Synopsys Designware Ethernet MAC"
> +	depends on DM_ETH && ETH_DESIGNWARE
> +	help
> +	  This driver provides Rockchip RK3288 network support based on the
> +	  Synopsys Designware driver.
> +
>   endif # NETDEVICES
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index 9a7bfc6..348e98b 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -34,6 +34,7 @@ obj-$(CONFIG_FTGMAC100) += ftgmac100.o
>   obj-$(CONFIG_FTMAC110) += ftmac110.o
>   obj-$(CONFIG_FTMAC100) += ftmac100.o
>   obj-$(CONFIG_GRETH) += greth.o
> +obj-$(CONFIG_GMAC_RK3288) += gmac_rk3288.o
>   obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
>   obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
>   obj-$(CONFIG_LAN91C96) += lan91c96.o
> diff --git a/drivers/net/gmac_rk3288.c b/drivers/net/gmac_rk3288.c
> new file mode 100644
> index 0000000..0c22756
> --- /dev/null
> +++ b/drivers/net/gmac_rk3288.c
> @@ -0,0 +1,154 @@
> +/*
> + * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + *
> + * Rockchip GMAC ethernet IP driver for U-Boot
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <clk.h>
> +#include <phy.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/arch/periph.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/grf_rk3288.h>
> +#include <dm/pinctrl.h>
> +#include <dt-bindings/clock/rk3288-cru.h>
> +#include "designware.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/*
> + * Platform data for the gmac
> + *
> + * dw_eth_pdata: Required platform data for designware driver (must be first)
> + */
> +struct gmac_rk3288_platdata {
> +	struct dw_eth_pdata dw_eth_pdata;
> +	int tx_delay;
> +	int rx_delay;
> +};
> +
> +static int gmac_rk3288_ofdata_to_platdata(struct udevice *dev)
> +{
> +	struct gmac_rk3288_platdata *pdata = dev_get_platdata(dev);
> +
> +	pdata->tx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
> +					 "tx-delay", 0x30);
> +	pdata->rx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
> +					 "rx-delay", 0x10);
> +
> +	return designware_eth_ofdata_to_platdata(dev);
> +}
> +
> +static int gmac_rk3288_fix_mac_speed(struct dw_eth_dev *priv)
> +{
> +	struct rk3288_grf *grf;
> +	int clk;
> +
> +	switch (priv->phydev->speed) {
> +	case 10:
> +		clk = GMAC_CLK_SEL_2_5M;
> +		break;
> +	case 100:
> +		clk = GMAC_CLK_SEL_25M;
> +		break;
> +	case 1000:
> +		clk = GMAC_CLK_SEL_125M;
> +		break;
> +	default:
> +		debug("Unknown phy speed: %d\n", priv->phydev->speed);
> +		return -EINVAL;
> +	}
> +
> +	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +	rk_clrsetreg(&grf->soc_con1,
> +		     GMAC_CLK_SEL_MASK << GMAC_CLK_SEL_SHIFT,
> +		     clk << GMAC_CLK_SEL_SHIFT);
> +
> +	return 0;
> +}
> +
> +static int gmac_rk3288_probe(struct udevice *dev)
> +{
> +	struct gmac_rk3288_platdata *pdata = dev_get_platdata(dev);
> +	struct rk3288_grf *grf;
> +	struct clk clk;
> +	int ret;
> +
> +	ret = clk_get_by_index(dev, 0, &clk);
> +	if (ret)
> +		return ret;
> +
> +	/* Since mac_clk is fed by an external clock we can use 0 here */
> +	ret = clk_set_rate(&clk, 0);
> +	if (ret)
> +		return ret;
> +
> +	/* Set to RGMII mode */
> +	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> +	rk_clrsetreg(&grf->soc_con1,
> +		     RMII_MODE_MASK << RMII_MODE_SHIFT |
> +		     GMAC_PHY_INTF_SEL_MASK << GMAC_PHY_INTF_SEL_SHIFT,
> +		     GMAC_PHY_INTF_SEL_RGMII << GMAC_PHY_INTF_SEL_SHIFT);
> +
> +	rk_clrsetreg(&grf->soc_con3,
> +		     RXCLK_DLY_ENA_GMAC_MASK <<  RXCLK_DLY_ENA_GMAC_SHIFT |
> +		     TXCLK_DLY_ENA_GMAC_MASK <<  TXCLK_DLY_ENA_GMAC_SHIFT |
> +		     CLK_RX_DL_CFG_GMAC_MASK <<  CLK_RX_DL_CFG_GMAC_SHIFT |
> +		     CLK_TX_DL_CFG_GMAC_MASK <<  CLK_TX_DL_CFG_GMAC_SHIFT,
> +		     RXCLK_DLY_ENA_GMAC_ENABLE << RXCLK_DLY_ENA_GMAC_SHIFT |
> +		     TXCLK_DLY_ENA_GMAC_ENABLE << TXCLK_DLY_ENA_GMAC_SHIFT |
> +		     pdata->rx_delay << CLK_RX_DL_CFG_GMAC_SHIFT |
> +		     pdata->tx_delay << CLK_TX_DL_CFG_GMAC_SHIFT);
> +
> +	return designware_eth_probe(dev);
> +}
> +
> +static int gmac_rk3288_eth_start(struct udevice *dev)
> +{
> +	struct eth_pdata *pdata = dev_get_platdata(dev);
> +	struct dw_eth_dev *priv = dev_get_priv(dev);
> +	int ret;
> +
> +	ret = designware_eth_init(priv, pdata->enetaddr);
> +	if (ret)
> +		return ret;
> +	ret = gmac_rk3288_fix_mac_speed(priv);
> +	if (ret)
> +		return ret;
> +	ret = designware_eth_enable(priv);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +const struct eth_ops gmac_rk3288_eth_ops = {
> +	.start			= gmac_rk3288_eth_start,
> +	.send			= designware_eth_send,
> +	.recv			= designware_eth_recv,
> +	.free_pkt		= designware_eth_free_pkt,
> +	.stop			= designware_eth_stop,
> +	.write_hwaddr		= designware_eth_write_hwaddr,
> +};
> +
> +static const struct udevice_id rk3288_gmac_ids[] = {
> +	{ .compatible = "rockchip,rk3288-gmac" },
> +	{ }
> +};
> +
> +U_BOOT_DRIVER(eth_gmac_rk3288) = {
> +	.name	= "gmac_rk3288",
> +	.id	= UCLASS_ETH,
> +	.of_match = rk3288_gmac_ids,
> +	.ofdata_to_platdata = gmac_rk3288_ofdata_to_platdata,
> +	.probe	= gmac_rk3288_probe,
> +	.ops	= &gmac_rk3288_eth_ops,
> +	.priv_auto_alloc_size = sizeof(struct dw_eth_dev),
> +	.platdata_auto_alloc_size = sizeof(struct gmac_rk3288_platdata),
> +	.flags = DM_FLAG_ALLOC_PRIV_DMA,
> +};
Simon Glass Jan. 13, 2017, 2:19 a.m. | #2
Hi David,

On 21 December 2016 at 07:55, David.Wu <david.wu@rock-chips.com> wrote:
> Hi Simon,
>
> Could you rename this driver file from rk3288 to rockchip,
> and the name of some common function?
> The other rockchip socs would use this driver as rk1108, etc.
>

I believe this has been done - if there are any issues, please let me know.

- Simon

>
> 在 2016/12/3 13:06, Simon Glass 写道:
>>
>> From: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
>>
>> Add a new driver for the GMAC ethernet interface present in Rockchip
>> RK3288 SOCs. This driver subclasses the generic design-ware driver to
>> add the glue needed specifically for Rockchip.
>>
>> Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
>> ---
>>
>> Changes in v4: None
>> Changes in v3:
>> - Add comments for struct gmac_rk3288_platdata
>> - Adjust binding to use r/tx-delay instead of r/tx_delay
>> - Sort includes
>> - Use debug() instead of printf() for error
>> - Use function calls instead of fix_mac_speed() hook
>> - Use new clk interface
>>
>> Changes in v2:
>> - Adjust to new hook name
>> - Fix various coding style nits
>>
>>   drivers/net/Kconfig       |   7 +++
>>   drivers/net/Makefile      |   1 +
>>   drivers/net/gmac_rk3288.c | 154
>> ++++++++++++++++++++++++++++++++++++++++++++++
>>   3 files changed, 162 insertions(+)
>>   create mode 100644 drivers/net/gmac_rk3288.c
>>
>> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
>> index f25d3ff..0027a2e 100644
>> --- a/drivers/net/Kconfig
>> +++ b/drivers/net/Kconfig
>> @@ -215,4 +215,11 @@ config PIC32_ETH
>>           This driver implements 10/100 Mbps Ethernet and MAC layer for
>>           Microchip PIC32 microcontrollers.
>>   +config GMAC_RK3288
>> +       bool "Rockchip RK3288 Synopsys Designware Ethernet MAC"
>> +       depends on DM_ETH && ETH_DESIGNWARE
>> +       help
>> +         This driver provides Rockchip RK3288 network support based on
>> the
>> +         Synopsys Designware driver.
>> +
>>   endif # NETDEVICES
>> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
>> index 9a7bfc6..348e98b 100644
>> --- a/drivers/net/Makefile
>> +++ b/drivers/net/Makefile
>> @@ -34,6 +34,7 @@ obj-$(CONFIG_FTGMAC100) += ftgmac100.o
>>   obj-$(CONFIG_FTMAC110) += ftmac110.o
>>   obj-$(CONFIG_FTMAC100) += ftmac100.o
>>   obj-$(CONFIG_GRETH) += greth.o
>> +obj-$(CONFIG_GMAC_RK3288) += gmac_rk3288.o
>>   obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
>>   obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
>>   obj-$(CONFIG_LAN91C96) += lan91c96.o
>> diff --git a/drivers/net/gmac_rk3288.c b/drivers/net/gmac_rk3288.c
>> new file mode 100644
>> index 0000000..0c22756
>> --- /dev/null
>> +++ b/drivers/net/gmac_rk3288.c
>> @@ -0,0 +1,154 @@
>> +/*
>> + * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
>> + *
>> + * SPDX-License-Identifier:    GPL-2.0+
>> + *
>> + * Rockchip GMAC ethernet IP driver for U-Boot
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <clk.h>
>> +#include <phy.h>
>> +#include <syscon.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/periph.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/grf_rk3288.h>
>> +#include <dm/pinctrl.h>
>> +#include <dt-bindings/clock/rk3288-cru.h>
>> +#include "designware.h"
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +/*
>> + * Platform data for the gmac
>> + *
>> + * dw_eth_pdata: Required platform data for designware driver (must be
>> first)
>> + */
>> +struct gmac_rk3288_platdata {
>> +       struct dw_eth_pdata dw_eth_pdata;
>> +       int tx_delay;
>> +       int rx_delay;
>> +};
>> +
>> +static int gmac_rk3288_ofdata_to_platdata(struct udevice *dev)
>> +{
>> +       struct gmac_rk3288_platdata *pdata = dev_get_platdata(dev);
>> +
>> +       pdata->tx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
>> +                                        "tx-delay", 0x30);
>> +       pdata->rx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
>> +                                        "rx-delay", 0x10);
>> +
>> +       return designware_eth_ofdata_to_platdata(dev);
>> +}
>> +
>> +static int gmac_rk3288_fix_mac_speed(struct dw_eth_dev *priv)
>> +{
>> +       struct rk3288_grf *grf;
>> +       int clk;
>> +
>> +       switch (priv->phydev->speed) {
>> +       case 10:
>> +               clk = GMAC_CLK_SEL_2_5M;
>> +               break;
>> +       case 100:
>> +               clk = GMAC_CLK_SEL_25M;
>> +               break;
>> +       case 1000:
>> +               clk = GMAC_CLK_SEL_125M;
>> +               break;
>> +       default:
>> +               debug("Unknown phy speed: %d\n", priv->phydev->speed);
>> +               return -EINVAL;
>> +       }
>> +
>> +       grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
>> +       rk_clrsetreg(&grf->soc_con1,
>> +                    GMAC_CLK_SEL_MASK << GMAC_CLK_SEL_SHIFT,
>> +                    clk << GMAC_CLK_SEL_SHIFT);
>> +
>> +       return 0;
>> +}
>> +
>> +static int gmac_rk3288_probe(struct udevice *dev)
>> +{
>> +       struct gmac_rk3288_platdata *pdata = dev_get_platdata(dev);
>> +       struct rk3288_grf *grf;
>> +       struct clk clk;
>> +       int ret;
>> +
>> +       ret = clk_get_by_index(dev, 0, &clk);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /* Since mac_clk is fed by an external clock we can use 0 here */
>> +       ret = clk_set_rate(&clk, 0);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /* Set to RGMII mode */
>> +       grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
>> +       rk_clrsetreg(&grf->soc_con1,
>> +                    RMII_MODE_MASK << RMII_MODE_SHIFT |
>> +                    GMAC_PHY_INTF_SEL_MASK << GMAC_PHY_INTF_SEL_SHIFT,
>> +                    GMAC_PHY_INTF_SEL_RGMII << GMAC_PHY_INTF_SEL_SHIFT);
>> +
>> +       rk_clrsetreg(&grf->soc_con3,
>> +                    RXCLK_DLY_ENA_GMAC_MASK <<  RXCLK_DLY_ENA_GMAC_SHIFT
>> |
>> +                    TXCLK_DLY_ENA_GMAC_MASK <<  TXCLK_DLY_ENA_GMAC_SHIFT
>> |
>> +                    CLK_RX_DL_CFG_GMAC_MASK <<  CLK_RX_DL_CFG_GMAC_SHIFT
>> |
>> +                    CLK_TX_DL_CFG_GMAC_MASK <<  CLK_TX_DL_CFG_GMAC_SHIFT,
>> +                    RXCLK_DLY_ENA_GMAC_ENABLE << RXCLK_DLY_ENA_GMAC_SHIFT
>> |
>> +                    TXCLK_DLY_ENA_GMAC_ENABLE << TXCLK_DLY_ENA_GMAC_SHIFT
>> |
>> +                    pdata->rx_delay << CLK_RX_DL_CFG_GMAC_SHIFT |
>> +                    pdata->tx_delay << CLK_TX_DL_CFG_GMAC_SHIFT);
>> +
>> +       return designware_eth_probe(dev);
>> +}
>> +
>> +static int gmac_rk3288_eth_start(struct udevice *dev)
>> +{
>> +       struct eth_pdata *pdata = dev_get_platdata(dev);
>> +       struct dw_eth_dev *priv = dev_get_priv(dev);
>> +       int ret;
>> +
>> +       ret = designware_eth_init(priv, pdata->enetaddr);
>> +       if (ret)
>> +               return ret;
>> +       ret = gmac_rk3288_fix_mac_speed(priv);
>> +       if (ret)
>> +               return ret;
>> +       ret = designware_eth_enable(priv);
>> +       if (ret)
>> +               return ret;
>> +
>> +       return 0;
>> +}
>> +
>> +const struct eth_ops gmac_rk3288_eth_ops = {
>> +       .start                  = gmac_rk3288_eth_start,
>> +       .send                   = designware_eth_send,
>> +       .recv                   = designware_eth_recv,
>> +       .free_pkt               = designware_eth_free_pkt,
>> +       .stop                   = designware_eth_stop,
>> +       .write_hwaddr           = designware_eth_write_hwaddr,
>> +};
>> +
>> +static const struct udevice_id rk3288_gmac_ids[] = {
>> +       { .compatible = "rockchip,rk3288-gmac" },
>> +       { }
>> +};
>> +
>> +U_BOOT_DRIVER(eth_gmac_rk3288) = {
>> +       .name   = "gmac_rk3288",
>> +       .id     = UCLASS_ETH,
>> +       .of_match = rk3288_gmac_ids,
>> +       .ofdata_to_platdata = gmac_rk3288_ofdata_to_platdata,
>> +       .probe  = gmac_rk3288_probe,
>> +       .ops    = &gmac_rk3288_eth_ops,
>> +       .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
>> +       .platdata_auto_alloc_size = sizeof(struct gmac_rk3288_platdata),
>> +       .flags = DM_FLAG_ALLOC_PRIV_DMA,
>> +};
>
>
>

Patch

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index f25d3ff..0027a2e 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -215,4 +215,11 @@  config PIC32_ETH
 	  This driver implements 10/100 Mbps Ethernet and MAC layer for
 	  Microchip PIC32 microcontrollers.
 
+config GMAC_RK3288
+	bool "Rockchip RK3288 Synopsys Designware Ethernet MAC"
+	depends on DM_ETH && ETH_DESIGNWARE
+	help
+	  This driver provides Rockchip RK3288 network support based on the
+	  Synopsys Designware driver.
+
 endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 9a7bfc6..348e98b 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -34,6 +34,7 @@  obj-$(CONFIG_FTGMAC100) += ftgmac100.o
 obj-$(CONFIG_FTMAC110) += ftmac110.o
 obj-$(CONFIG_FTMAC100) += ftmac100.o
 obj-$(CONFIG_GRETH) += greth.o
+obj-$(CONFIG_GMAC_RK3288) += gmac_rk3288.o
 obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
 obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
 obj-$(CONFIG_LAN91C96) += lan91c96.o
diff --git a/drivers/net/gmac_rk3288.c b/drivers/net/gmac_rk3288.c
new file mode 100644
index 0000000..0c22756
--- /dev/null
+++ b/drivers/net/gmac_rk3288.c
@@ -0,0 +1,154 @@ 
+/*
+ * (C) Copyright 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Rockchip GMAC ethernet IP driver for U-Boot
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <clk.h>
+#include <phy.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk3288.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+#include "designware.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Platform data for the gmac
+ *
+ * dw_eth_pdata: Required platform data for designware driver (must be first)
+ */
+struct gmac_rk3288_platdata {
+	struct dw_eth_pdata dw_eth_pdata;
+	int tx_delay;
+	int rx_delay;
+};
+
+static int gmac_rk3288_ofdata_to_platdata(struct udevice *dev)
+{
+	struct gmac_rk3288_platdata *pdata = dev_get_platdata(dev);
+
+	pdata->tx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+					 "tx-delay", 0x30);
+	pdata->rx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+					 "rx-delay", 0x10);
+
+	return designware_eth_ofdata_to_platdata(dev);
+}
+
+static int gmac_rk3288_fix_mac_speed(struct dw_eth_dev *priv)
+{
+	struct rk3288_grf *grf;
+	int clk;
+
+	switch (priv->phydev->speed) {
+	case 10:
+		clk = GMAC_CLK_SEL_2_5M;
+		break;
+	case 100:
+		clk = GMAC_CLK_SEL_25M;
+		break;
+	case 1000:
+		clk = GMAC_CLK_SEL_125M;
+		break;
+	default:
+		debug("Unknown phy speed: %d\n", priv->phydev->speed);
+		return -EINVAL;
+	}
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->soc_con1,
+		     GMAC_CLK_SEL_MASK << GMAC_CLK_SEL_SHIFT,
+		     clk << GMAC_CLK_SEL_SHIFT);
+
+	return 0;
+}
+
+static int gmac_rk3288_probe(struct udevice *dev)
+{
+	struct gmac_rk3288_platdata *pdata = dev_get_platdata(dev);
+	struct rk3288_grf *grf;
+	struct clk clk;
+	int ret;
+
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (ret)
+		return ret;
+
+	/* Since mac_clk is fed by an external clock we can use 0 here */
+	ret = clk_set_rate(&clk, 0);
+	if (ret)
+		return ret;
+
+	/* Set to RGMII mode */
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->soc_con1,
+		     RMII_MODE_MASK << RMII_MODE_SHIFT |
+		     GMAC_PHY_INTF_SEL_MASK << GMAC_PHY_INTF_SEL_SHIFT,
+		     GMAC_PHY_INTF_SEL_RGMII << GMAC_PHY_INTF_SEL_SHIFT);
+
+	rk_clrsetreg(&grf->soc_con3,
+		     RXCLK_DLY_ENA_GMAC_MASK <<  RXCLK_DLY_ENA_GMAC_SHIFT |
+		     TXCLK_DLY_ENA_GMAC_MASK <<  TXCLK_DLY_ENA_GMAC_SHIFT |
+		     CLK_RX_DL_CFG_GMAC_MASK <<  CLK_RX_DL_CFG_GMAC_SHIFT |
+		     CLK_TX_DL_CFG_GMAC_MASK <<  CLK_TX_DL_CFG_GMAC_SHIFT,
+		     RXCLK_DLY_ENA_GMAC_ENABLE << RXCLK_DLY_ENA_GMAC_SHIFT |
+		     TXCLK_DLY_ENA_GMAC_ENABLE << TXCLK_DLY_ENA_GMAC_SHIFT |
+		     pdata->rx_delay << CLK_RX_DL_CFG_GMAC_SHIFT |
+		     pdata->tx_delay << CLK_TX_DL_CFG_GMAC_SHIFT);
+
+	return designware_eth_probe(dev);
+}
+
+static int gmac_rk3288_eth_start(struct udevice *dev)
+{
+	struct eth_pdata *pdata = dev_get_platdata(dev);
+	struct dw_eth_dev *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = designware_eth_init(priv, pdata->enetaddr);
+	if (ret)
+		return ret;
+	ret = gmac_rk3288_fix_mac_speed(priv);
+	if (ret)
+		return ret;
+	ret = designware_eth_enable(priv);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+const struct eth_ops gmac_rk3288_eth_ops = {
+	.start			= gmac_rk3288_eth_start,
+	.send			= designware_eth_send,
+	.recv			= designware_eth_recv,
+	.free_pkt		= designware_eth_free_pkt,
+	.stop			= designware_eth_stop,
+	.write_hwaddr		= designware_eth_write_hwaddr,
+};
+
+static const struct udevice_id rk3288_gmac_ids[] = {
+	{ .compatible = "rockchip,rk3288-gmac" },
+	{ }
+};
+
+U_BOOT_DRIVER(eth_gmac_rk3288) = {
+	.name	= "gmac_rk3288",
+	.id	= UCLASS_ETH,
+	.of_match = rk3288_gmac_ids,
+	.ofdata_to_platdata = gmac_rk3288_ofdata_to_platdata,
+	.probe	= gmac_rk3288_probe,
+	.ops	= &gmac_rk3288_eth_ops,
+	.priv_auto_alloc_size = sizeof(struct dw_eth_dev),
+	.platdata_auto_alloc_size = sizeof(struct gmac_rk3288_platdata),
+	.flags = DM_FLAG_ALLOC_PRIV_DMA,
+};