From patchwork Tue May 15 13:58:22 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhao X-Patchwork-Id: 8655 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 0960023E13 for ; Tue, 15 May 2012 13:59:20 +0000 (UTC) Received: from mail-wi0-f176.google.com (mail-wi0-f176.google.com [209.85.212.176]) by fiordland.canonical.com (Postfix) with ESMTP id 00EB1A185E1 for ; Tue, 15 May 2012 13:59:19 +0000 (UTC) Received: by wibhn14 with SMTP id hn14so4689327wib.17 for ; Tue, 15 May 2012 06:59:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf :x-spamscore:x-bigfish:x-forefront-antispam-report:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :mime-version:content-type:x-originatororg:x-gm-message-state; bh=OSpKXcYXJ0knjWP1I3aXvdgAGl44yuGyWdlMM7KZcIo=; b=p5EVjGYo1r8r1My5PO0H5QhpK1qUERhsm3bOpgsgixZabwfeX4wQWM1DQvSpLbC0aD pCuipucpVFE71JubqZc5KlVGn0fnqThzDQMtRckYyVQd4FfpZqkI+iKRUAwQjk6VpUql bLVqtzBf6QVpeHyxEphbkuowIko17RkU8Zip0rYemxSV7q+kwtLngto0Qr/iva0Tafbn n/iI39ywncerG0Min98qSSUO/KTUIsJ1Gz3dYaIudjvsFrMFIu7raejhJujKMzqnkzJL 4DizO38te1CT3CJCSXTOLT0Y2o2b4zcpYWLueIHNogRge6Bld2wYfaGFUVviryl1hDrN L+Mw== Received: by 10.50.203.39 with SMTP id kn7mr7036850igc.53.1337090359209; Tue, 15 May 2012 06:59:19 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp422516ibd; Tue, 15 May 2012 06:59:18 -0700 (PDT) Received: by 10.216.27.199 with SMTP id e49mr7868847wea.45.1337090357846; Tue, 15 May 2012 06:59:17 -0700 (PDT) Received: from am1outboundpool.messaging.microsoft.com (am1ehsobe001.messaging.microsoft.com. [213.199.154.204]) by mx.google.com with ESMTPS id cf9si6235679wib.8.2012.05.15.06.59.17 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 15 May 2012 06:59:17 -0700 (PDT) Received-SPF: neutral (google.com: 213.199.154.204 is neither permitted nor denied by best guess record for domain of B20223@freescale.com) client-ip=213.199.154.204; Authentication-Results: mx.google.com; spf=neutral (google.com: 213.199.154.204 is neither permitted nor denied by best guess record for domain of B20223@freescale.com) smtp.mail=B20223@freescale.com Received: from mail99-am1-R.bigfish.com (10.3.201.242) by AM1EHSOBE006.bigfish.com (10.3.204.26) with Microsoft SMTP Server id 14.1.225.23; Tue, 15 May 2012 13:59:11 +0000 Received: from mail99-am1 (localhost [127.0.0.1]) by mail99-am1-R.bigfish.com (Postfix) with ESMTP id 58314C0071; Tue, 15 May 2012 13:59:11 +0000 (UTC) X-SpamScore: 3 X-BigFish: VS3(zcb8kzzz1202hzz8275bhz2dh2a8h668h839hd24he5bh) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail99-am1 (localhost.localdomain [127.0.0.1]) by mail99-am1 (MessageSwitch) id 1337090349684371_12314; Tue, 15 May 2012 13:59:09 +0000 (UTC) Received: from AM1EHSMHS007.bigfish.com (unknown [10.3.201.225]) by mail99-am1.bigfish.com (Postfix) with ESMTP id 95B811A006C; Tue, 15 May 2012 13:59:09 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS007.bigfish.com (10.3.207.107) with Microsoft SMTP Server (TLS) id 14.1.225.23; Tue, 15 May 2012 13:59:09 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.2.298.5; Tue, 15 May 2012 08:59:12 -0500 Received: from b20223-02.ap.freescale.net (b20223-02.ap.freescale.net [10.192.242.124]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id q4FDwjZP003112; Tue, 15 May 2012 08:59:09 -0500 (CDT) From: Richard Zhao To: , CC: , , , , , , , , , Richard Zhao Subject: [PATCH v1 6/7] ARM: imx6q: add anatop initialization for usb controllers Date: Tue, 15 May 2012 21:58:22 +0800 Message-ID: <1337090303-16046-7-git-send-email-richard.zhao@freescale.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1337090303-16046-1-git-send-email-richard.zhao@freescale.com> References: <1337090303-16046-1-git-send-email-richard.zhao@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-Gm-Message-State: ALoCoQlDHo2E+Rs8rSAotDeKoR3/QR/q3+i8cItXNyOkA4hX6kY0iqBxepCqIqP1QUt55Tty6JXQ Signed-off-by: Richard Zhao --- arch/arm/mach-imx/mach-imx6q.c | 60 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 60 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 74e44d3..4530c45 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -82,6 +83,63 @@ static void __init imx6q_sabrelite_init(void) ksz9021rn_phy_fixup); } +static void __init imx6q_post_populate(void) +{ + u32 val; + +#define HW_ANADIG_USB2_CHRG_DETECT (0x00000210) +#define BM_ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000 +#define BM_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000 + +#define HW_ANADIG_USB2_PLL_480_CTRL (0x00000020) +#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000 +#define BM_ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000 +#define BM_ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000 +#define BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040 + + /* Some phy and power's special controls for host1 + * 1. The external charger detector needs to be disabled + * or the signal at DP will be poor + * 2. The PLL's power and output to usb for host 1 + * is totally controlled by IC, so the Software only needs + * to enable them at initializtion. + */ + + anatop_write_reg(NULL, HW_ANADIG_USB2_CHRG_DETECT, + BM_ANADIG_USB2_CHRG_DETECT_EN_B | + BM_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, + ~0); + anatop_write_reg(NULL, HW_ANADIG_USB2_PLL_480_CTRL, 0, + BM_ANADIG_USB2_PLL_480_CTRL_BYPASS); + + val = BM_ANADIG_USB2_PLL_480_CTRL_ENABLE | + BM_ANADIG_USB2_PLL_480_CTRL_POWER | + BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS; + anatop_write_reg(NULL, HW_ANADIG_USB2_PLL_480_CTRL, val, val); + + /* Some phy and power's special controls for otg + * 1. The external charger detector needs to be disabled + * or the signal at DP will be poor + * 2. The EN_USB_CLKS is always enabled. + * The PLL's power is controlled by usb and others who + * use pll3 too. + */ +#define HW_ANADIG_USB1_CHRG_DETECT (0x000001b0) +#define BM_ANADIG_USB1_CHRG_DETECT_EN_B 0x00100000 +#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B 0x00080000 + +#define HW_ANADIG_USB1_PLL_480_CTRL (0x00000010) +#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 + + anatop_write_reg(NULL, HW_ANADIG_USB1_CHRG_DETECT, + BM_ANADIG_USB1_CHRG_DETECT_EN_B + | BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B, + ~0); + anatop_write_reg(NULL, HW_ANADIG_USB1_PLL_480_CTRL, + BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS, + BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS); +} + static void __init imx6q_init_machine(void) { /* @@ -95,6 +153,8 @@ static void __init imx6q_init_machine(void) of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + imx6q_post_populate(); + imx6q_pm_init(); }