diff mbox

[GCC/ARM,gcc-5/6-branch,ping] Fix PR77904: callee-saved register trashed when clobbering sp

Message ID f83fde54-c264-bb8b-3f49-36d4b85171c3@foss.arm.com
State New
Headers show

Commit Message

Thomas Preudhomme Dec. 6, 2016, 11:38 a.m. UTC 
Ping?

Best regards,

Thomas

On 30/11/16 10:44, Thomas Preudhomme wrote:
> Sorry, the bug cannot be reproduced on gcc-5-branch so it's probably better to

> only do a backport to gcc-6-branch.

>

> Ok for a backport to gcc-6-branch?

>

> Best regards,

>

> Thomas

>

> On 30/11/16 10:42, Thomas Preudhomme wrote:

>> Hi,

>>

>> Is this ok to backport to gcc-5-branch and gcc-6-branch? Patch applies cleanly

>> (patches attached for reference).

>>

>>

>> 2016-11-30 Thomas Preud'homme <thomas.preudhomme@arm.com>

>>

>>     Backport from mainline

>>     2016-11-22  Thomas Preud'homme  <thomas.preudhomme@arm.com>

>>

>>     gcc/

>>     PR target/77904

>>     * config/arm/arm.c (thumb1_compute_save_reg_mask): Mark frame pointer

>>     in save register mask if it is needed.

>>

>>     gcc/testsuite/

>>     PR target/77904

>>     * gcc.target/arm/pr77904.c: New test.

>>

>>

>> Best regards,

>>

>> Thomas

>>

>>

>> On 22/11/16 10:45, Thomas Preudhomme wrote:

>>> On 17/11/16 09:11, Kyrill Tkachov wrote:

>>>>

>>>> On 17/11/16 08:56, Thomas Preudhomme wrote:

>>>>> On 16/11/16 10:30, Kyrill Tkachov wrote:

>>>>>> Hi Thomas,

>>>>>>

>>>>>> On 03/11/16 16:52, Thomas Preudhomme wrote:

>>>>>>> Hi,

>>>>>>>

>>>>>>> When using a callee-saved register to save the frame pointer the Thumb-1

>>>>>>> prologue fails to save the callee-saved register before that. For ARM and

>>>>>>> Thumb-2 targets the frame pointer is handled as a special case but

>>>>>>> nothing is

>>>>>>> done for Thumb-1 targets. This patch adds the same logic for Thumb-1

>>>>>>> targets.

>>>>>>>

>>>>>>> ChangeLog entries are as follow:

>>>>>>>

>>>>>>> *** gcc/ChangeLog ***

>>>>>>>

>>>>>>> 2016-11-02  Thomas Preud'homme <thomas.preudhomme@arm.com>

>>>>>>>

>>>>>>>         PR target/77904

>>>>>>>         * config/arm/arm.c (thumb1_compute_save_reg_mask): mark frame

>>>>>>> pointer

>>>>>>>         in save register mask if it is needed.

>>>>>>>

>>>>>>

>>>>>> s/mark/Mark/

>>>>>>

>>>>>>>

>>>>>>> *** gcc/testsuite/ChangeLog ***

>>>>>>>

>>>>>>> 2016-11-02  Thomas Preud'homme <thomas.preudhomme@arm.com>

>>>>>>>

>>>>>>>         PR target/77904

>>>>>>>         * gcc.target/arm/pr77904.c: New test.

>>>>>>>

>>>>>>>

>>>>>>> Testing: Testsuite shows no regression when run with arm-none-eabi GCC

>>>>>>> cross-compiler for Cortex-M0 target.

>>>>>>>

>>>>>>> Is this ok for trunk?

>>>>>>>

>>>>>>

>>>>>> I'd ask for a bootstrap, but this code is Thumb-1 only so it wouldn't affect

>>>>>> anything.

>>>>>

>>>>> I can bootstrap for armv4t with --with-mode=thumb which would at least

>>>>> exercise the path. I'll try such a bootstrap on qemu.

>>>>>

>>>>

>>>> If you can get it to work, then yes please.

>>>

>>> Bootstrap came back clean so I've committed the patch (r242693). Thanks!

>>>

>>> Best regards,

>>>

>>> Thomas
diff mbox

Patch

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 47171b99682207226aa4f9a76d4dfb54d6c2814b..86df1c0366be6c4b9b4ebf76821a8100c4e9fc16 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -575,9 +575,9 @@ 
 ;;  (plus (reg rN) (reg sp)) into (reg rN).  In this case reload will
 ;; put the duplicated register first, and not try the commutative version.
 (define_insn_and_split "*arm_addsi3"
-  [(set (match_operand:SI          0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,r ,k ,r ,k,k,r ,k ,r")
-        (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,rk,k ,rk,k,r,rk,k ,rk")
-                 (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,Pj,Pj,L ,L,L,PJ,PJ,?n")))]
+  [(set (match_operand:SI          0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,k ,r ,k ,r ,k,k,r ,k ,r")
+	(plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,r ,rk,k ,rk,k,r,rk,k ,rk")
+		 (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,rI,Pj,Pj,L ,L,L,PJ,PJ,?n")))]
   "TARGET_32BIT"
   "@
    add%?\\t%0, %0, %2
@@ -587,6 +587,7 @@ 
    add%?\\t%0, %1, %2
    add%?\\t%0, %1, %2
    add%?\\t%0, %2, %1
+   add%?\\t%0, %1, %2
    addw%?\\t%0, %1, %2
    addw%?\\t%0, %1, %2
    sub%?\\t%0, %1, #%n2
@@ -606,10 +607,10 @@ 
 		      operands[1], 0);
   DONE;
   "
-  [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,16")
+  [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,4,16")
    (set_attr "predicable" "yes")
-   (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no")
-   (set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*")
+   (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no,no")
+   (set_attr "arch" "t2,t2,t2,t2,*,*,*,a,t2,t2,*,*,a,t2,t2,*")
    (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
 		      (const_string "alu_imm")
 		      (const_string "alu_sreg")))
diff --git a/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c
new file mode 100644
index 0000000000000000000000000000000000000000..8313f2199122be153a737946e817a5e3bee60372
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c
@@ -0,0 +1,12 @@ 
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! arm_cortex_m } { "-mthumb" } } */
+
+/* Below code used to trigger an ICE due to missing constraints for
+   sp = fp + cst pattern.  */
+
+void fiq_handler (void) __attribute__((interrupt ("FIQ")));
+
+void
+fiq_handler (void)
+{
+}