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[192.237.175.120]) by mx.google.com with ESMTPS id b132si17269605iob.231.2016.12.07.04.36.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Dec 2016 04:36:06 -0800 (PST) Received-SPF: neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.237.175.120 is neither permitted nor denied by best guess record for domain of xen-devel-bounces@lists.xen.org) smtp.mailfrom=xen-devel-bounces@lists.xen.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cEbQP-0006Im-Sv; Wed, 07 Dec 2016 12:34:17 +0000 Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cEbQP-0006HG-8N for xen-devel@lists.xen.org; Wed, 07 Dec 2016 12:34:17 +0000 Received: from [85.158.143.35] by server-7.bemta-6.messagelabs.com id C5/29-29519-8C108485; Wed, 07 Dec 2016 12:34:16 +0000 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRWlGSWpSXmKPExsVysyfVTfcIo0e EweUT2hZLPi5mcWD0OLr7N1MAYxRrZl5SfkUCa8bim/PZC77KViybtoGtgXGTeBcjF4eQwGZG id1Tt7FBOKcZJRa+7WDpYuTkYBPQlLjz+RMTiC0iIC1x7fNlRhCbWcBB4s3He2A1wgL+EuePn GIGsVkEVCXe9D4Dq+cVcJWYNqGHFcSWEJCTOHlsMpjNCRS/9fUvWK+QgIvE16ZlLBMYuRcwMq xi1ChOLSpLLdI1NNFLKspMzyjJTczM0TU0MNPLTS0uTkxPzUlMKtZLzs/dxAj0MAMQ7GC8vjH gEKMkB5OSKO+uCe4RQnxJ+SmVGYnFGfFFpTmpxYcYZTg4lCR4FzF4RAgJFqWmp1akZeYAQw0m LcHBoyTCu+8/UCtvcUFibnFmOkTqFKOilDjvXJA+AZBERmkeXBssvC8xykoJ8zICHSLEU5Bal JtZgir/ilGcg1FJmJcLZApPZl4J3PRXQIuZgBbPuwG2uCQRISXVwNgopn3h6VvVq82LfnwJdv Dk2zzB2E2mYId9s+aWZfy+v2Wdblo6tj+Nc5+jK3zswMKdGz5dOSUQeH6tk/8S9kdld5k4kqW 3LvSbkcj66c/lH6acSY6nnmzTLAvM7pzJsO6b/d9OzeJIToGj3M5TP4sWMs89nC0q8zDu3EeJ 3r3Xz9/VdmQ9/kCJpTgj0VCLuag4EQCjwXMJagIAAA== X-Env-Sender: julien.grall@arm.com X-Msg-Ref: server-9.tower-21.messagelabs.com!1481114052!46989061!1 X-Originating-IP: [217.140.101.70] X-SpamReason: No, hits=0.5 required=7.0 tests=BODY_RANDOM_LONG X-StarScan-Received: X-StarScan-Version: 9.0.16; banners=-,-,- X-VirusChecked: Checked Received: (qmail 48309 invoked from network); 7 Dec 2016 12:34:12 -0000 Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by server-9.tower-21.messagelabs.com with SMTP; 7 Dec 2016 12:34:12 -0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CF73D154D; Wed, 7 Dec 2016 04:34:11 -0800 (PST) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.218.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3D95E3F477; Wed, 7 Dec 2016 04:34:11 -0800 (PST) From: Julien Grall To: xen-devel@lists.xen.org Date: Wed, 7 Dec 2016 12:33:53 +0000 Message-Id: <1481114033-11024-14-git-send-email-julien.grall@arm.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1481114033-11024-1-git-send-email-julien.grall@arm.com> References: <1481114033-11024-1-git-send-email-julien.grall@arm.com> Cc: Julien Grall , sstabellini@kernel.org Subject: [Xen-devel] [PATCH 13/13] xen/arm: vgic-v3: Allow AArch32 guest booting with GICv3 X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" AArch32 guest will use co-processor registers to access the GICv3 (see 8.5 in IHI 0069C). Some of the registers have to be trapped and emulated (e.g ICC_SGI1R), this is the purpose of this patch. The rest of the emulation already supports access required for AArch32 so nothing has to be changed there. Note this is only enabling 32-bit guest using GICv3 on Xen ARM64. Further work would be required to compile GICv3 and vGICv3 for Xen ARM32. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/traps.c | 12 ++++++++++++ xen/arch/arm/vgic-v3.c | 20 ++++++++++++++++++++ xen/include/asm-arm/cpregs.h | 3 +++ xen/include/asm-arm/perfc_defn.h | 2 ++ 4 files changed, 37 insertions(+) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 1fe02cb..eb85d92 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -1876,6 +1876,18 @@ static void do_cp15_64(struct cpu_user_regs *regs, break; /* + * HCR_EL2.FMO or HCR_EL2.IMO + * + * GIC Architecture Specification (IHI 0069C): Section 4.6.3 + */ + case HSR_CPREG64(ICC_SGI1R): + case HSR_CPREG64(ICC_ASGI1R): + case HSR_CPREG64(ICC_SGI0R): + if ( !vgic_emulate(regs, hsr) ) + return inject_undef_exception(regs, hsr); + break; + + /* * CPTR_EL2.T{0..9,12..13} * * ARMv7 (DDI 0406C.b): B1.14.12 diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c index f23135d..22c8ce0 100644 --- a/xen/arch/arm/vgic-v3.c +++ b/xen/arch/arm/vgic-v3.c @@ -1335,12 +1335,32 @@ static bool vgic_v3_emulate_sysreg(struct cpu_user_regs *regs, union hsr hsr) } } +static bool vgic_v3_emulate_cp64(struct cpu_user_regs *regs, union hsr hsr) +{ + struct hsr_cp64 cp64 = hsr.cp64; + + if ( cp64.read ) + perfc_incr(vgic_cp64_reads); + else + perfc_incr(vgic_cp64_writes); + + switch ( hsr.bits & HSR_CP64_REGS_MASK ) + { + case HSR_CPREG64(ICC_SGI1R): + return vreg_emulate_cp64(regs, hsr, vgic_v3_emulate_sgi1r); + default: + return false; + } +} + static bool vgic_v3_emulate_reg(struct cpu_user_regs *regs, union hsr hsr) { switch (hsr.ec) { case HSR_EC_SYSREG: return vgic_v3_emulate_sysreg(regs, hsr); + case HSR_EC_CP15_64: + return vgic_v3_emulate_cp64(regs, hsr); default: return false; } diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h index e5cb00c..af45ec7 100644 --- a/xen/include/asm-arm/cpregs.h +++ b/xen/include/asm-arm/cpregs.h @@ -246,6 +246,9 @@ /* CP15 CR11: DMA Operations for TCM Access */ /* CP15 CR12: */ +#define ICC_SGI1R p15,0,c12 /* Interrupt Controller SGI Group 1 */ +#define ICC_ASGI1R p15,1,c12 /* Interrupt Controller Alias SGI Group 1 Register */ +#define ICC_SGI0R p15,2,c12 /* Interrupt Controller SGI Group 0 */ #define VBAR p15,0,c12,c0,0 /* Vector Base Address Register */ #define HVBAR p15,4,c12,c0,0 /* Hyp. Vector Base Address Register */ diff --git a/xen/include/asm-arm/perfc_defn.h b/xen/include/asm-arm/perfc_defn.h index 69fabe7..5f957ee 100644 --- a/xen/include/asm-arm/perfc_defn.h +++ b/xen/include/asm-arm/perfc_defn.h @@ -38,6 +38,8 @@ PERFCOUNTER(vgicd_reads, "vgicd: read") PERFCOUNTER(vgicd_writes, "vgicd: write") PERFCOUNTER(vgicr_reads, "vgicr: read") PERFCOUNTER(vgicr_writes, "vgicr: write") +PERFCOUNTER(vgic_cp64_reads, "vgic: cp64 read") +PERFCOUNTER(vgic_cp64_writes, "vgic: cp64 write") PERFCOUNTER(vgic_sysreg_reads, "vgic: sysreg read") PERFCOUNTER(vgic_sysreg_writes, "vgic: sysreg write") PERFCOUNTER(vgic_sgi_list , "vgic: SGI send to list")