| Message ID | 20250330210717.46080-7-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add support for DU and DSI on the Renesas RZ/V2H(P) SoC | expand |
On Sun, Mar 30, 2025 at 10:07:02PM +0100, Prabhakar wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of > the RZ/G2L SoC. While the LINK registers are the same for both SoCs, the > D-PHY registers differ. Additionally, the number of resets for DSI on > RZ/V2H(P) is two compared to three on the RZ/G2L. > > To accommodate these differences, a SoC-specific > `renesas,r9a09g057-mipi-dsi` compatible string has been added for the > RZ/V2H(P) SoC. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > .../bindings/display/bridge/renesas,dsi.yaml | 117 +++++++++++++----- > 1 file changed, 87 insertions(+), 30 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > index e08c24633926..501239f7adab 100644 > --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > @@ -14,16 +14,16 @@ description: | > RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with > up to four data lanes. > > -allOf: > - - $ref: /schemas/display/dsi-controller.yaml# > - > properties: > compatible: > - items: > - - enum: > - - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} > - - renesas,r9a07g054-mipi-dsi # RZ/V2L > - - const: renesas,rzg2l-mipi-dsi > + oneOf: > + - items: > + - enum: > + - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} > + - renesas,r9a07g054-mipi-dsi # RZ/V2L > + - const: renesas,rzg2l-mipi-dsi > + > + - const: renesas,r9a09g057-mipi-dsi # RZ/V2H(P) I guess this will grow, so just use enum here. Otherwise people keep adding const every time they add new model. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
Hi Krzysztof, Thank you for the review. On Mon, Mar 31, 2025 at 9:26 AM Krzysztof Kozlowski <krzk@kernel.org> wrote: > > On Sun, Mar 30, 2025 at 10:07:02PM +0100, Prabhakar wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of > > the RZ/G2L SoC. While the LINK registers are the same for both SoCs, the > > D-PHY registers differ. Additionally, the number of resets for DSI on > > RZ/V2H(P) is two compared to three on the RZ/G2L. > > > > To accommodate these differences, a SoC-specific > > `renesas,r9a09g057-mipi-dsi` compatible string has been added for the > > RZ/V2H(P) SoC. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > .../bindings/display/bridge/renesas,dsi.yaml | 117 +++++++++++++----- > > 1 file changed, 87 insertions(+), 30 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > > index e08c24633926..501239f7adab 100644 > > --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > > +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml > > @@ -14,16 +14,16 @@ description: | > > RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with > > up to four data lanes. > > > > -allOf: > > - - $ref: /schemas/display/dsi-controller.yaml# > > - > > properties: > > compatible: > > - items: > > - - enum: > > - - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} > > - - renesas,r9a07g054-mipi-dsi # RZ/V2L > > - - const: renesas,rzg2l-mipi-dsi > > + oneOf: > > + - items: > > + - enum: > > + - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} > > + - renesas,r9a07g054-mipi-dsi # RZ/V2L > > + - const: renesas,rzg2l-mipi-dsi > > + > > + - const: renesas,r9a09g057-mipi-dsi # RZ/V2H(P) > > I guess this will grow, so just use enum here. Otherwise people keep > adding const every time they add new model. > Agreed, I will add it as an enum here as RZ/V2N will follow this where the IP blocks are identical. > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Cheers, Prabhakar
diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml index e08c24633926..501239f7adab 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml @@ -14,16 +14,16 @@ description: | RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with up to four data lanes. -allOf: - - $ref: /schemas/display/dsi-controller.yaml# - properties: compatible: - items: - - enum: - - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} - - renesas,r9a07g054-mipi-dsi # RZ/V2L - - const: renesas,rzg2l-mipi-dsi + oneOf: + - items: + - enum: + - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} + - renesas,r9a07g054-mipi-dsi # RZ/V2L + - const: renesas,rzg2l-mipi-dsi + + - const: renesas,r9a09g057-mipi-dsi # RZ/V2H(P) reg: maxItems: 1 @@ -49,34 +49,56 @@ properties: - const: debug clocks: - items: - - description: DSI D-PHY PLL multiplied clock - - description: DSI D-PHY system clock - - description: DSI AXI bus clock - - description: DSI Register access clock - - description: DSI Video clock - - description: DSI D-PHY Escape mode transmit clock + oneOf: + - items: + - description: DSI D-PHY PLL multiplied clock + - description: DSI D-PHY system clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock + - items: + - description: DSI D-PHY PLL multiplied clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock clock-names: - items: - - const: pllclk - - const: sysclk - - const: aclk - - const: pclk - - const: vclk - - const: lpclk + oneOf: + - items: + - const: pllclk + - const: sysclk + - const: aclk + - const: pclk + - const: vclk + - const: lpclk + - items: + - const: pllclk + - const: aclk + - const: pclk + - const: vclk + - const: lpclk resets: - items: - - description: MIPI_DSI_CMN_RSTB - - description: MIPI_DSI_ARESET_N - - description: MIPI_DSI_PRESET_N + oneOf: + - items: + - description: MIPI_DSI_CMN_RSTB + - description: MIPI_DSI_ARESET_N + - description: MIPI_DSI_PRESET_N + - items: + - description: MIPI_DSI_ARESET_N + - description: MIPI_DSI_PRESET_N reset-names: - items: - - const: rst - - const: arst - - const: prst + oneOf: + - items: + - const: rst + - const: arst + - const: prst + - items: + - const: arst + - const: prst power-domains: maxItems: 1 @@ -130,6 +152,41 @@ required: additionalProperties: false +allOf: + - $ref: ../dsi-controller.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-mipi-dsi + then: + properties: + clocks: + maxItems: 5 + + clock-names: + maxItems: 5 + + resets: + maxItems: 2 + + reset-names: + maxItems: 2 + else: + properties: + clocks: + minItems: 6 + + clock-names: + minItems: 6 + + resets: + minItems: 3 + + reset-names: + minItems: 3 + examples: - | #include <dt-bindings/clock/r9a07g044-cpg.h>