From patchwork Mon Dec 12 18:47:42 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 87731 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp1799686qgi; Mon, 12 Dec 2016 10:48:02 -0800 (PST) X-Received: by 10.84.136.75 with SMTP id 69mr185083286plk.52.1481568482723; Mon, 12 Dec 2016 10:48:02 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id 1si44461514pgy.294.2016.12.12.10.48.02 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Dec 2016 10:48:02 -0800 (PST) Received-SPF: pass (google.com: domain of gdb-patches-return-135772-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org; spf=pass (google.com: domain of gdb-patches-return-135772-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gdb-patches-return-135772-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :content-type; q=dns; s=default; b=iqqi/E1KA5GM8uNtRknOiPnIXWb34 HHQu1fFMpP6nVU2ngrbJ8854uUEx17a74akhMXhvXSRqwquQtMM6PbxOKCMo1yMy gO22IpWIBR/XKIqnrbzl0i7L/mHULgyFLVxYOoA1/nvcEzEe7zQSEDKD0HSh130d e3L5g6m3rCuIbk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :content-type; s=default; bh=3LibxVyYBmfLzQH3g8np+Zb8FTQ=; b=qoD j+47hoh8Nt3o3PLtNp+IteLo2AEuDY8Z9Jt3BXo+1x+y03Nr8eAzBWfyct5A/27/ TB1Dx5aTNOJcwuXw/kIT6m2qRl29BiKx+Rh9dRV+4CPLE/WKemihR9M9XrZ2YK5A V7Ms5Yqi2svzr2HQxtMTMsFGsqeUp9llLjnwlJBU= Received: (qmail 84707 invoked by alias); 12 Dec 2016 18:47:55 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 83810 invoked by uid 89); 12 Dec 2016 18:47:54 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=2627, sim_cpu X-HELO: mail-yb0-f173.google.com Received: from mail-yb0-f173.google.com (HELO mail-yb0-f173.google.com) (209.85.213.173) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 12 Dec 2016 18:47:44 +0000 Received: by mail-yb0-f173.google.com with SMTP id v78so5200499ybe.3 for ; Mon, 12 Dec 2016 10:47:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=shKDBkLTfYXZzyYLUrtPwAZoev+RJ2Y0f2r2TQi1O6k=; b=RDxop0ZNm/AodzDU3CCCgDmnq/1L5iB8PyS38pWxklRkqd9gatAkLdkXvBzbUtLDXg 5K0UEXL6SQB6s+ZnunR5ckRKJgSm01FFv0Llj22yIY/wE2L3fndj7BdxMcwQjxbOgJWn ICCQ5vw/lswRFX09AsbZfDyooc0gh7pT+Lkxhg4pqhkiQm03qLM0AZVqdGCGDRREAJcO n1GPpZoaglTNJ7w5Ia+4gei33Y1dNEJ6epyb9xC27Q1AvAWb4WpseBQMa1R7QiIsU37t wky+kkNEmwlxRbnPPdR7GDV6OskixgLUahYenixix8CEWyAlqex0OK2HrtfI9nlLHwIf JFpg== X-Gm-Message-State: AKaTC001L77SkQ2WwO6+KDJIuncAm9Es8HuhVTJpyW25dm4eok/vmgGDpyzrSzZ25Sa5gQRv2/McGkKS3d7r+Y/l X-Received: by 10.37.246.9 with SMTP id t9mr49366842ybd.107.1481568462473; Mon, 12 Dec 2016 10:47:42 -0800 (PST) MIME-Version: 1.0 Received: by 10.129.92.4 with HTTP; Mon, 12 Dec 2016 10:47:42 -0800 (PST) From: Jim Wilson Date: Mon, 12 Dec 2016 10:47:42 -0800 Message-ID: Subject: [PATCH] fix for aarch64 sim adds64 bug To: gdb-patches@sourceware.org, Nick Clifton The set_flags_for_add64 function is computing carry out wrong. It may also be computing overflow wrong. I replaced it with a copy of the set_flags_for_sub64 function which is OK, just negating the tests for value2. I added a testcase to verify the change. The testcase fails without the patch, and works with the patch. I also verified with a gcc C testsuite run. The failures drop from 2710 to 2627. The new testcase requires my previous patch to fix the aarch64/testutils.inc file. Jim 2016-12-12 Jim Wilson * sim/aarch64/simulator.c (NEG, POS): Move before set_flags_for_add64. (set_flags_for_add64): Replace with a modified copy of set_flags_for_sub64. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index 34fd17d..e6406dc 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -1659,55 +1659,34 @@ set_flags_for_add32 (sim_cpu *cpu, int32_t value1, int32_t value2) aarch64_set_CPSR (cpu, flags); } +#define NEG(a) (((a) & signbit) == signbit) +#define POS(a) (((a) & signbit) == 0) + static void set_flags_for_add64 (sim_cpu *cpu, uint64_t value1, uint64_t value2) { - int64_t sval1 = value1; - int64_t sval2 = value2; - uint64_t result = value1 + value2; - int64_t sresult = sval1 + sval2; - uint32_t flags = 0; + uint64_t result = value1 + value2; + uint32_t flags = 0; + uint64_t signbit = 1ULL << 63; if (result == 0) flags |= Z; - if (result & (1ULL << 63)) + if (NEG (result)) flags |= N; - if (sval1 < 0) - { - if (sval2 < 0) - { - /* Negative plus a negative. Overflow happens if - the result is greater than either of the operands. */ - if (sresult > sval1 || sresult > sval2) - flags |= V; - } - /* else Negative plus a positive. Overflow cannot happen. */ - } - else /* value1 is +ve. */ - { - if (sval2 < 0) - { - /* Overflow can only occur if we computed "0 - MININT". */ - if (sval1 == 0 && sval2 == (1LL << 63)) - flags |= V; - } - else - { - /* Postive plus positive - overflow has happened if the - result is smaller than either of the operands. */ - if (result < value1 || result < value2) - flags |= V | C; - } - } + if ( (NEG (value1) && NEG (value2)) + || (NEG (value1) && POS (result)) + || (NEG (value2) && POS (result))) + flags |= C; + + if ( (NEG (value1) && NEG (value2) && POS (result)) + || (POS (value1) && POS (value2) && NEG (result))) + flags |= V; aarch64_set_CPSR (cpu, flags); } -#define NEG(a) (((a) & signbit) == signbit) -#define POS(a) (((a) & signbit) == 0) - static void set_flags_for_sub32 (sim_cpu *cpu, uint32_t value1, uint32_t value2) {