| Message ID | 20250417065354.311617-3-sakari.ailus@linux.intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | CCS PLL fixes and improvements | expand |
Hi Sakari, Thank you for the patch. On Thu, Apr 17, 2025 at 09:53:45AM +0300, Sakari Ailus wrote: > The ccs_pll_calculate_vt_tree() function does a search over possible VT > PLL configurations to find the "best" one. If the sensor did not support > odd pre-PLL divisors and the minimum value (with constraints) wasn't 1, > other even values could have errorneously searched (and selected) for the > pre-PLL divisor. Fix this. Same comments as for 01/11. You can add my R-b tag if you address the issues in the same way. > Fixes: 415ddd993978 ("media: ccs-pll: Split limits and PLL configuration into front and back parts") > Cc: stable@vger.kernel.org > Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> > --- > drivers/media/i2c/ccs-pll.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c > index e516ed23e899..2399cd6509b7 100644 > --- a/drivers/media/i2c/ccs-pll.c > +++ b/drivers/media/i2c/ccs-pll.c > @@ -397,6 +397,8 @@ static int ccs_pll_calculate_vt_tree(struct device *dev, > min_pre_pll_clk_div = max_t(u16, min_pre_pll_clk_div, > pll->ext_clk_freq_hz / > lim_fr->max_pll_ip_clk_freq_hz); > + if (!(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER)) > + min_pre_pll_clk_div = clk_div_even(min_pre_pll_clk_div); > > dev_dbg(dev, "vt min/max_pre_pll_clk_div: %u,%u\n", > min_pre_pll_clk_div, max_pre_pll_clk_div);
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index e516ed23e899..2399cd6509b7 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -397,6 +397,8 @@ static int ccs_pll_calculate_vt_tree(struct device *dev, min_pre_pll_clk_div = max_t(u16, min_pre_pll_clk_div, pll->ext_clk_freq_hz / lim_fr->max_pll_ip_clk_freq_hz); + if (!(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER)) + min_pre_pll_clk_div = clk_div_even(min_pre_pll_clk_div); dev_dbg(dev, "vt min/max_pre_pll_clk_div: %u,%u\n", min_pre_pll_clk_div, max_pre_pll_clk_div);
The ccs_pll_calculate_vt_tree() function does a search over possible VT PLL configurations to find the "best" one. If the sensor did not support odd pre-PLL divisors and the minimum value (with constraints) wasn't 1, other even values could have errorneously searched (and selected) for the pre-PLL divisor. Fix this. Fixes: 415ddd993978 ("media: ccs-pll: Split limits and PLL configuration into front and back parts") Cc: stable@vger.kernel.org Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> --- drivers/media/i2c/ccs-pll.c | 2 ++ 1 file changed, 2 insertions(+)