[1/2] S390: Optimize atomic macros.

Message ID 485d2d38-26ae-b941-e55d-a58f7559049b@linux.vnet.ibm.com
State New
Headers show

Commit Message

Stefan Liebler Dec. 16, 2016, 5:08 p.m.
On 12/09/2016 04:16 PM, Stefan Liebler wrote:
> On 11/24/2016 01:51 PM, Torvald Riegel wrote:

>> On Wed, 2016-11-23 at 16:09 +0100, Stefan Liebler wrote:

>>> The atomic_compare_and_exchange_val_acq macro is now implemented with

>>> gcc __sync_val_compare_and_swap instead of an inline assembly with

>>> compare-and-swap instruction.

>>

>> Can you use the new GCC atomic builtins, or are they still insufficient

>> on s390?

>>

>> Related to that, can you define USE_ATOMIC_COMPILER_BUILTINS to 1?

>> Generally, this is where we want to get to, so that we have to maintain

>> as few atomic operations as possible.

>>

>> Also note that we'll be phasing out the old-style glibc atomics

>> eventually and use the new C11-like atomics.

> I've activated it and tried an example like this (also compare it with

> pthread_once):

> int

> foo (int *lock)

> {

>   int val, newval;

>   val = atomic_load_acquire (lock);

>   do

>     {

>       newval = val | 123;

>     }

>   while (!atomic_compare_exchange_weak_acquire (lock, &val, newval));

>

>   return 0;

> }

>

> The assembly produced by GCC 5.4/6.2 contains a new stack-frame, the old

> value is stored and loaded to/from the stack-frame before the

> cs-instruction.

> After the cs, the old value is stored again and reloaded if a further

> round of cs is needed.

> The condition-code of cs is extracted into a register and then compared

> to determine if a further round of cs is needed.

>

> The cs-instruction itself updates the old-value-register and a

> conditional jump can be used for a further round.

>

> An upstream gcc produces better code, but it's also not perfect!

> I've already informed Andreas Krebbel.

>

> Thus I won't set USE_ATOMIC_COMPILER_BUILTINS to 1 now.

> And if gcc is fixed, I will activate it only for this version and newer.

>

>>

>>> The memory is compared against expected OLDVAL before using

>>> compare-and-swap

>>> instruction in case of OLDVAL is constant at compile time.  This is

>>> used in

>>> various locking code.  If the lock is already aquired, another cpu

>>> has not to

>>> exclusively lock the memory.  If OLDVAL is not constant the

>>> compare-and-swap

>>> instruction is used directly as the usages of this macro usually load

>>> the

>>> current value in front of this macro.

>>

>> Generally, I think the compiler should do these optimizations (under the

>> assumption that we drive these using builtin_expect and the like).  If

>> GCC not doing these (with new _atomic* builtins), is there a patch about

>> that or at least a BZ?  I'd be okay with accepting an intermediate

>> solution that optimizes atomics in glibc, but I'd want to make this

>> clear in code comments and reference the GCC BZ that makes the

>> improvement request; this ensures that we can drop the glibc hack once

>> GCC does what you want it to do.

>>

> No. This comparision will not be included in the gcc builtins as they

> are intended to only be compare-and-swap instruction.

>

>> For this particular case, I'm hoping we can just fix this in the

>> compiler.

>>

>> Regarding your patch, the compiler barrier is in the wrong position for

>> an acquire MO operation; for the new C11-like atomics, it would be

>> unnecessary because we only guarantee relaxed MO in the failure case.

>>

> If *mem is equal to constant oldval, the sync builtin is considered as

> full barrier after loading *mem. If *mem is not equal to constant

> oldval, you are right there is no barrier after the load and the

> compiler could hoist memory accesses before the load of mem!?

> Thus I can add the compiler barrier in the else path like below.

> +#define atomic_compare_and_exchange_val_acq(mem, newval, oldval)\

> +  ({ __asm__ __volatile__ ("" ::: "memory");            \

> +    __typeof (*(mem)) __atg1_ret;                \

> +    if (!__builtin_constant_p (oldval)                \

> +    || __builtin_expect ((__atg1_ret = *(mem))        \

> +                 == (oldval), 1))            \

> +      __atg1_ret = __sync_val_compare_and_swap ((mem), (oldval),\

> +                        (newval));    \

> +    else                            \

> +      __asm__ __volatile__ ("" ::: "memory");            \

> +    __atg1_ret; })

> The intention of the full barrier before the load and the if-statement

> is to "force" the load and compare directly before cs instruction.

>

>>> The same applies to atomic_compare_and_exchange_bool_acq which wasn't

>>> defined before.  Now it is implemented with gcc

>>> __sync_bool_compare_and_swap.

>>> If the macro is used as condition in an if/while expression, the

>>> condition

>>> code is used to e.g. jump directly to another code sequence.  Before

>>> this

>>> change, the old value returned by compare-and-swap instruction was

>>> compared

>>> with given OLDVAL to determine if e.g. a jump is needed.

> I will add the barrier here in the same way as mention above.

>>>

>>> The atomic_exchange_acq macro is now using the load-and-and

>>> instruction for a

>>> constant zero value instead of a compare-and-swap loop.  This

>>> instruction is

>>> available on a z196 zarch and higher cpus.  This is e.g. used in

>>> unlocking code.

>>

>> See above.  This should be fixed in the compiler.

> There is no sync-builtin which can be used for exchanging the value as

> done in atomic_exchange_acq. Thus I have to do it in this glibc-macro.

> But you are right, the compiler can fix this for c11 builtin

> __atomic_exchange_n.

> But even if it is fixed in a new version, builds with older compilers

> won't use the load-and-and instruction.

> In case of e.g. lll_unlock, an additional register loaded with the

> old-value and an additional jump is needed.

>

>>

>>> The newly defined atomic_exchange_and_add macro is implemented with gcc

>>> builtin __sync_fetch_and_add which uses load-and-add instruction on

>>> z196 zarch

>>> and higher cpus instead of a loop with compare-and-swap instruction.

>>> The same applies to atomic_or_val, atomic_and_val, ... macros, which use

>>> the appropiate z196 instruction.

>>

>> Can you just use the new _atomic builtins?  The compiler should just

>> give use _atomic* builtins that are optimized, and we should use them.

>>

> I've checked, if __atomic_fetch_or|add use lao|laa instructions.

> And yes they use it, too.

> As there are issues with the __atomic* builtins as mentioned above,

> the usage of the __sync_fetch_* is currently needed here.

> I don't intend to use a mix of __sync and __atomic builtins.

>

>> With that in place, we could just implement the old-style glibc atomic

>> operations based on the _atomic* builtins, and have much less code to

>> maintain.

>>

> Yes, you are right, this is the correct way in future.

> I saw at least aarch64 is doing that this way.

>

>>> The macros lll_trylock, lll_cond_trylock are extended by an

>>> __glibc_unlikely

>>> hint. With the hint gcc on s390 emits code in e.g. pthread_mutex_trylock

>>> which does not use jumps in case the lock is free.  Without the hint

>>> it had

>>> to jump if the lock was free.

>>

>> I think it's debatable whether trylock should expect the lock to be

>> free.  OTOH, if it's not free, I guess that we should be in the slow

>> path in most use cases anyway.  Either way, I think it's a choice we

>> should make generically for all architectures, and I want to keep

>> arch-specific code to a minimum.  Thus, please split this out and

>> propose it for the generic lowlevellock.

>>

> Okay. I will send a separate patch to propose this change for common-code.

>



Here is an update of this patch. The compiler barrier in 
atomic_compare_and_exchange_val_acq and 
atomic_compare_and_exchange_bool_acq is now fixed.
The hints in macros lll_trylock/lll_cond_trylock are seperated and 
posted here:
"[PATCH] Add __glibc_unlikely hint in lll_trylock, lll_cond_trylock."
https://www.sourceware.org/ml/libc-alpha/2016-12/msg00451.html

The patch-file contains the updated ChangeLog.

Bye.
Stefan

Comments

Torvald Riegel Dec. 16, 2016, 7:15 p.m. | #1
On Fri, 2016-12-16 at 18:08 +0100, Stefan Liebler wrote:
> On 12/09/2016 04:16 PM, Stefan Liebler wrote:

> > On 11/24/2016 01:51 PM, Torvald Riegel wrote:

> >> On Wed, 2016-11-23 at 16:09 +0100, Stefan Liebler wrote:

> >>> The atomic_compare_and_exchange_val_acq macro is now implemented with

> >>> gcc __sync_val_compare_and_swap instead of an inline assembly with

> >>> compare-and-swap instruction.

> >>

> >> Can you use the new GCC atomic builtins, or are they still insufficient

> >> on s390?

> >>

> >> Related to that, can you define USE_ATOMIC_COMPILER_BUILTINS to 1?

> >> Generally, this is where we want to get to, so that we have to maintain

> >> as few atomic operations as possible.

> >>

> >> Also note that we'll be phasing out the old-style glibc atomics

> >> eventually and use the new C11-like atomics.

> > I've activated it and tried an example like this (also compare it with

> > pthread_once):

> > int

> > foo (int *lock)

> > {

> >   int val, newval;

> >   val = atomic_load_acquire (lock);


Note that this can be a relaxed MO load.

> >   do

> >     {

> >       newval = val | 123;

> >     }

> >   while (!atomic_compare_exchange_weak_acquire (lock, &val, newval));

> >

> >   return 0;

> > }

> >

> > The assembly produced by GCC 5.4/6.2 contains a new stack-frame, the old

> > value is stored and loaded to/from the stack-frame before the

> > cs-instruction.

> > After the cs, the old value is stored again and reloaded if a further

> > round of cs is needed.

> > The condition-code of cs is extracted into a register and then compared

> > to determine if a further round of cs is needed.

> >

> > The cs-instruction itself updates the old-value-register and a

> > conditional jump can be used for a further round.


That indeed sounds like the compiler misses quite a few optimizations.
Is this the same if you use a relaxed load before the loop?

> > An upstream gcc produces better code, but it's also not perfect!


How much closer to "perfect" is it?

> > I've already informed Andreas Krebbel.

> >

> > Thus I won't set USE_ATOMIC_COMPILER_BUILTINS to 1 now.

> > And if gcc is fixed, I will activate it only for this version and newer.


That is understandable.

I'd still prefer if you could include a summary of the information you
provided above as a comment in the code (or open up a bug with the
information, so that it doesn't get lost, or add something to the
Concurrency wiki page, or ...).

> >>

> >>> The memory is compared against expected OLDVAL before using

> >>> compare-and-swap

> >>> instruction in case of OLDVAL is constant at compile time.  This is

> >>> used in

> >>> various locking code.  If the lock is already aquired, another cpu

> >>> has not to

> >>> exclusively lock the memory.  If OLDVAL is not constant the

> >>> compare-and-swap

> >>> instruction is used directly as the usages of this macro usually load

> >>> the

> >>> current value in front of this macro.

> >>

> >> Generally, I think the compiler should do these optimizations (under the

> >> assumption that we drive these using builtin_expect and the like).  If

> >> GCC not doing these (with new _atomic* builtins), is there a patch about

> >> that or at least a BZ?  I'd be okay with accepting an intermediate

> >> solution that optimizes atomics in glibc, but I'd want to make this

> >> clear in code comments and reference the GCC BZ that makes the

> >> improvement request; this ensures that we can drop the glibc hack once

> >> GCC does what you want it to do.

> >>

> > No. This comparision will not be included in the gcc builtins as they

> > are intended to only be compare-and-swap instruction.


They are not just that, actually.  We expect the builtins to have the
effect of a CAS when executed, but under the hood that's more than just
issuing the instruction.  For example, we expect the compiler to pick
suitable registers and do something efficient with the flags.

I agree that your case could be considered borderline, because it's
"outside" of the CAS (as opposed to an LL/SC machine where the check
could be after the LL, or something like that).  However, you only do
the optimization for constants.

> >> For this particular case, I'm hoping we can just fix this in the

> >> compiler.

> >>

> >> Regarding your patch, the compiler barrier is in the wrong position for

> >> an acquire MO operation; for the new C11-like atomics, it would be

> >> unnecessary because we only guarantee relaxed MO in the failure case.

> >>

> > If *mem is equal to constant oldval, the sync builtin is considered as

> > full barrier after loading *mem. If *mem is not equal to constant

> > oldval, you are right there is no barrier after the load and the

> > compiler could hoist memory accesses before the load of mem!?


If the true branch of the conditional is taken, the compiler won't hoist
the load before the __sync builtin, because it needs the load to
determine whether the __sync should actually happen.

> > Thus I can add the compiler barrier in the else path like below.


Yes, and given that s390 is TSO-like (IIRC), this would be like an
acquire barrier.

However, the more I think about this, the more I'm worried that
transforming an idempotent CAS into just a load might mess with the
assurances we give regarding the C11 memory model.  At least in C11, the
memory model gives stronger guarantees for an idempotent CAS than for a
load, I believe; for example, that it potentially extends release
sequences, it has different effects on ordering, etc.

What you're proposing is effectively a different s390-atomics-to-C11
mapping.  We should be *very* sure that this is a valid mapping before
we make such a change.  I'm in no position to assess that, simply
because I don't know enough about the s390 model.  Are you confident
enough to make this assessment, and can you show why it's correct?

What you are proposing is a special case, I'd argue (eg, because of
expecting a constant).  I think it would be better if you propose
changes to what you think the uses of this optimization are because we
can much more easily argue about correctness of concrete uses of this.

> > +#define atomic_compare_and_exchange_val_acq(mem, newval, oldval)\

> > +  ({ __asm__ __volatile__ ("" ::: "memory");            \

> > +    __typeof (*(mem)) __atg1_ret;                \

> > +    if (!__builtin_constant_p (oldval)                \

> > +    || __builtin_expect ((__atg1_ret = *(mem))        \

> > +                 == (oldval), 1))            \

> > +      __atg1_ret = __sync_val_compare_and_swap ((mem), (oldval),\

> > +                        (newval));    \

> > +    else                            \

> > +      __asm__ __volatile__ ("" ::: "memory");            \

> > +    __atg1_ret; })

> > The intention of the full barrier before the load and the if-statement

> > is to "force" the load and compare directly before cs instruction.


But that wouldn't be required for correctness, or do you have something
additional in mind that you want to achieve?  Or is affecting compiler
optimizations the intent here?

> >>> The same applies to atomic_compare_and_exchange_bool_acq which wasn't

> >>> defined before.  Now it is implemented with gcc

> >>> __sync_bool_compare_and_swap.

> >>> If the macro is used as condition in an if/while expression, the

> >>> condition

> >>> code is used to e.g. jump directly to another code sequence.  Before

> >>> this

> >>> change, the old value returned by compare-and-swap instruction was

> >>> compared

> >>> with given OLDVAL to determine if e.g. a jump is needed.

> > I will add the barrier here in the same way as mention above.

> >>>

> >>> The atomic_exchange_acq macro is now using the load-and-and

> >>> instruction for a

> >>> constant zero value instead of a compare-and-swap loop.  This

> >>> instruction is

> >>> available on a z196 zarch and higher cpus.  This is e.g. used in

> >>> unlocking code.

> >>

> >> See above.  This should be fixed in the compiler.

> > There is no sync-builtin which can be used for exchanging the value as

> > done in atomic_exchange_acq. Thus I have to do it in this glibc-macro.

> > But you are right, the compiler can fix this for c11 builtin

> > __atomic_exchange_n.

> > But even if it is fixed in a new version, builds with older compilers

> > won't use the load-and-and instruction.


First, can we just use the __atomic builtins instead of __sync?  For the
minimum compiler version current glibc supports, what is the code
generated for __atomic_fetch_add?  IIRC, the minimum GCC version we
support already supports the __atomic builtins.  I'd be surprised if
__sync is optimized better than __atomic.

I'll also say again that especially the exchange to 0 should be a
compiler optimization.  If there is truly a reason to apply the stop-gap
measure that you propose, we must have a GCC bug report for this so we
can track when this happens, and the number of this GCC bug must go into
a comment you add to the code.

> > In case of e.g. lll_unlock, an additional register loaded with the

> > old-value and an additional jump is needed.


That is a comparison against the CAS version?

> >>

> >>> The newly defined atomic_exchange_and_add macro is implemented with gcc

> >>> builtin __sync_fetch_and_add which uses load-and-add instruction on

> >>> z196 zarch

> >>> and higher cpus instead of a loop with compare-and-swap instruction.

> >>> The same applies to atomic_or_val, atomic_and_val, ... macros, which use

> >>> the appropiate z196 instruction.

> >>

> >> Can you just use the new _atomic builtins?  The compiler should just

> >> give use _atomic* builtins that are optimized, and we should use them.

> >>

> > I've checked, if __atomic_fetch_or|add use lao|laa instructions.

> > And yes they use it, too.

> > As there are issues with the __atomic* builtins as mentioned above,

> > the usage of the __sync_fetch_* is currently needed here.

> > I don't intend to use a mix of __sync and __atomic builtins.


Why?  __atomic is much better specified.  __sync is like a seq_cst
__atomic, essentially.

> >> With that in place, we could just implement the old-style glibc atomic

> >> operations based on the _atomic* builtins, and have much less code to

> >> maintain.

> >>

> > Yes, you are right, this is the correct way in future.

> > I saw at least aarch64 is doing that this way.

> >

> >>> The macros lll_trylock, lll_cond_trylock are extended by an

> >>> __glibc_unlikely

> >>> hint. With the hint gcc on s390 emits code in e.g. pthread_mutex_trylock

> >>> which does not use jumps in case the lock is free.  Without the hint

> >>> it had

> >>> to jump if the lock was free.

> >>

> >> I think it's debatable whether trylock should expect the lock to be

> >> free.  OTOH, if it's not free, I guess that we should be in the slow

> >> path in most use cases anyway.  Either way, I think it's a choice we

> >> should make generically for all architectures, and I want to keep

> >> arch-specific code to a minimum.  Thus, please split this out and

> >> propose it for the generic lowlevellock.

> >>

> > Okay. I will send a separate patch to propose this change for common-code.

> >

> 

> 

> Here is an update of this patch. The compiler barrier in 

> atomic_compare_and_exchange_val_acq and 

> atomic_compare_and_exchange_bool_acq is now fixed.

> The hints in macros lll_trylock/lll_cond_trylock are seperated and 

> posted here:

> "[PATCH] Add __glibc_unlikely hint in lll_trylock, lll_cond_trylock."

> https://www.sourceware.org/ml/libc-alpha/2016-12/msg00451.html

> 

> The patch-file contains the updated ChangeLog.


Thanks.  See my comments above.
Torvald Riegel Dec. 16, 2016, 7:18 p.m. | #2
On Fri, 2016-12-16 at 18:08 +0100, Stefan Liebler wrote:
> On 12/09/2016 04:16 PM, Stefan Liebler wrote:

> > On 11/24/2016 01:51 PM, Torvald Riegel wrote:

> >> On Wed, 2016-11-23 at 16:09 +0100, Stefan Liebler wrote:

> >>> The atomic_compare_and_exchange_val_acq macro is now implemented with

> >>> gcc __sync_val_compare_and_swap instead of an inline assembly with

> >>> compare-and-swap instruction.

> >>

> >> Can you use the new GCC atomic builtins, or are they still insufficient

> >> on s390?

> >>

> >> Related to that, can you define USE_ATOMIC_COMPILER_BUILTINS to 1?

> >> Generally, this is where we want to get to, so that we have to maintain

> >> as few atomic operations as possible.

> >>

> >> Also note that we'll be phasing out the old-style glibc atomics

> >> eventually and use the new C11-like atomics.

> > I've activated it and tried an example like this (also compare it with

> > pthread_once):

> > int

> > foo (int *lock)

> > {

> >   int val, newval;

> >   val = atomic_load_acquire (lock);

> >   do

> >     {

> >       newval = val | 123;

> >     }

> >   while (!atomic_compare_exchange_weak_acquire (lock, &val, newval));

> >

> >   return 0;

> > }

> >

> > The assembly produced by GCC 5.4/6.2 contains a new stack-frame, the old

> > value is stored and loaded to/from the stack-frame before the

> > cs-instruction.

> > After the cs, the old value is stored again and reloaded if a further

> > round of cs is needed.

> > The condition-code of cs is extracted into a register and then compared

> > to determine if a further round of cs is needed.


Having read your other message, did you try with an int* or volatile
int* lock?
Stefan Liebler Feb. 27, 2017, 11:36 a.m. | #3
This patch activates c11 atomic builtins by defining
USE_ATOMIC_COMPILER_BUILTINS to 1.
Note:
E.g. in nptl/pthread_key_delete.c if compiled with GCCs 6 and before,
an extra stack-frame is generated and the old value is stored on stack
before cs instruction but it never loads this value from stack.
An unreleased GCC 7 omit those stack operations.

E.g. in nptl/pthread_once.c the condition code of cs instruction is
evaluated by a sequence of ipm, sra, compare and jump instructions
instead of one conditional jump instruction.
This also occurs with an unreleased GCC 7.

These shortcomings does not really hurt.  Nevertheless, the gcc guys are
investigating those ones and plan to fix them before GCC 7 release.

The atomic_fetch_abc_def c11 builtins are now using load-and-abc
instructions on z196 zarch and higher cpus instead of a loop
with compare-and-swap instruction.

Some of the non-c11 atomic macros from include/atomic.h are now
implemented with help of the c11 atomic builtins.
The other non-c11 atomic macros are using the macros defined here.

Optimizations like using load-and-and for exchanging memory to zero
will be done by GCC in future.

ChangeLog:

	* sysdeps/s390/atomic-machine.h
	(USE_ATOMIC_COMPILER_BUILTINS): Define to 1.
	(__arch_compare_and_exchange_val_8_acq,
	__arch_compare_and_exchange_val_16_acq,
	__arch_compare_and_exchange_val_32_acq,
	__arch_compare_and_exchange_val_64_acq):
	Delete macro.
	(atomic_compare_and_exchange_val_acq,
	atomic_compare_and_exchange_val_rel,
	atomic_compare_and_exchange_bool_acq,
	catomic_compare_and_exchange_bool_acq,
	atomic_exchange_acq, atomic_exchange_rel,
	atomic_exchange_and_add_acq,
	atomic_exchange_and_add_rel,
	catomic_exchange_and_add, atomic_or_val,
	atomic_or, catomic_or, atomic_bit_test_set,
	atomic_and_val, atomic_and, catomic_and):
	Define macros with help of c11 atomic builtins.commit 187e63cf8411585313051f020a39f8b6010280a9
Author: Stefan Liebler <stli@linux.vnet.ibm.com>
Date:   Mon Feb 27 12:23:32 2017 +0100

    S390: Optimize atomic macros.
    
    This patch activates c11 atomic builtins by defining
    USE_ATOMIC_COMPILER_BUILTINS to 1.
    Note:
    E.g. in nptl/pthread_key_delete.c if compiled with GCCs 6 and before,
    an extra stack-frame is generated and the old value is stored on stack
    before cs instruction but it never loads this value from stack.
    An unreleased GCC 7 omit those stack operations.
    
    E.g. in nptl/pthread_once.c the condition code of cs instruction is
    evaluated by a sequence of ipm, sra, compare and jump instructions instead
    of one conditional jump instruction.  This also occurs with an unreleased
    GCC 7.
    
    These shortcomings does not really hurt.  Nevertheless, the gcc guys are
    investigating those ones and plan to fix them before GCC 7 release.
    
    The atomic_fetch_abc_def c11 builtins are now using load-and-abc instructions
    on z196 zarch and higher cpus instead of a loop with compare-and-swap
    instruction.
    
    Some of the non-c11 atomic macros from include/atomic.h are now implemented
    with help of the c11 atomic builtins.  The other non-c11 atomic macros
    are using the macros defined here.
    
    ChangeLog:
    
    	* sysdeps/s390/atomic-machine.h
    	(USE_ATOMIC_COMPILER_BUILTINS): Define to 1.
    	(__arch_compare_and_exchange_val_8_acq,
    	__arch_compare_and_exchange_val_16_acq,
    	__arch_compare_and_exchange_val_32_acq,
    	__arch_compare_and_exchange_val_64_acq):
    	Delete macro.
    	(atomic_compare_and_exchange_val_acq,
    	atomic_compare_and_exchange_val_rel,
    	atomic_compare_and_exchange_bool_acq,
    	catomic_compare_and_exchange_bool_acq,
    	atomic_exchange_acq, atomic_exchange_rel,
    	atomic_exchange_and_add_acq,
    	atomic_exchange_and_add_rel,
    	catomic_exchange_and_add, atomic_or_val,
    	atomic_or, catomic_or, atomic_bit_test_set,
    	atomic_and_val, atomic_and, catomic_and):
    	Define macros with help of c11 atomic builtins.

diff --git a/sysdeps/s390/atomic-machine.h b/sysdeps/s390/atomic-machine.h
index 211d3d6..6f0a6fe 100644
--- a/sysdeps/s390/atomic-machine.h
+++ b/sysdeps/s390/atomic-machine.h
@@ -43,78 +43,117 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
-#define USE_ATOMIC_COMPILER_BUILTINS 0
+/* Activate all c11 atomic builtins.
 
+   Note:
+   E.g. in nptl/pthread_key_delete.c if compiled with GCCs 6 and before,
+   an extra stack-frame is generated and the old value is stored on stack
+   before cs instruction but it never loads this value from stack.
+   An unreleased GCC 7 omit those stack operations.
 
-#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
-  (abort (), (__typeof (*mem)) 0)
+   E.g. in nptl/pthread_once.c the condition code of cs instruction is
+   evaluated by a sequence of ipm, sra, compare and jump instructions instead
+   of one conditional jump instruction.  This also occurs with an unreleased
+   GCC 7.
 
-#define __arch_compare_and_exchange_val_16_acq(mem, newval, oldval) \
-  (abort (), (__typeof (*mem)) 0)
-
-#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
-  ({ __typeof (mem) __archmem = (mem);					      \
-     __typeof (*mem) __archold = (oldval);				      \
-     __asm__ __volatile__ ("cs %0,%2,%1"				      \
-			   : "+d" (__archold), "=Q" (*__archmem)	      \
-			   : "d" (newval), "m" (*__archmem) : "cc", "memory" );	\
-     __archold; })
+   The atomic_fetch_abc_def c11 builtins are now using load-and-abc instructions
+   on z196 zarch and higher cpus instead of a loop with compare-and-swap
+   instruction.  */
+#define USE_ATOMIC_COMPILER_BUILTINS 1
 
 #ifdef __s390x__
 # define __HAVE_64B_ATOMICS 1
-# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
-  ({ __typeof (mem) __archmem = (mem);					      \
-     __typeof (*mem) __archold = (oldval);				      \
-     __asm__ __volatile__ ("csg %0,%2,%1"				      \
-			   : "+d" (__archold), "=Q" (*__archmem)	      \
-			   : "d" ((long) (newval)), "m" (*__archmem) : "cc", "memory" ); \
-     __archold; })
 #else
 # define __HAVE_64B_ATOMICS 0
-/* For 31 bit we do not really need 64-bit compare-and-exchange. We can
-   implement them by use of the csd instruction. The straightforward
-   implementation causes warnings so we skip the definition for now.  */
-# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
-  (abort (), (__typeof (*mem)) 0)
 #endif
 
+/* Implement some of the non-c11 atomic macros from include/atomic.h
+   with help of the c11 atomic builtins.  The other non-c11 atomic macros
+   are using the macros defined here.  */
+
+/* Atomically store NEWVAL in *MEM if *MEM is equal to OLDVAL.
+   Return the old *MEM value.  */
+#define atomic_compare_and_exchange_val_acq(mem, newval, oldval)	\
+  ({ __atomic_check_size((mem));					\
+    typeof ((__typeof (*(mem))) *(mem)) __atg1_oldval = (oldval);	\
+    __atomic_compare_exchange_n (mem, (void *) &__atg1_oldval,		\
+				 newval, 1, __ATOMIC_ACQUIRE,		\
+				 __ATOMIC_RELAXED);			\
+    __atg1_oldval; })
+#define atomic_compare_and_exchange_val_rel(mem, newval, oldval)	\
+  ({ __atomic_check_size((mem));					\
+    typeof ((__typeof (*(mem))) *(mem)) __atg1_2_oldval = (oldval);	\
+    __atomic_compare_exchange_n (mem, (void *) &__atg1_2_oldval,	\
+				 newval, 1, __ATOMIC_RELEASE,		\
+				 __ATOMIC_RELAXED);			\
+    __atg1_2_oldval; })
+
+/* Atomically store NEWVAL in *MEM if *MEM is equal to OLDVAL.
+   Return zero if *MEM was changed or non-zero if no exchange happened.  */
+#define atomic_compare_and_exchange_bool_acq(mem, newval, oldval)	\
+  ({ __atomic_check_size((mem));					\
+    typeof ((__typeof (*(mem))) *(mem)) __atg2_oldval = (oldval);	\
+    !__atomic_compare_exchange_n (mem, (void *) &__atg2_oldval, newval,	\
+				  1, __ATOMIC_ACQUIRE,			\
+				  __ATOMIC_RELAXED); })
+#define catomic_compare_and_exchange_bool_acq(mem, newval, oldval)	\
+  atomic_compare_and_exchange_bool_acq (mem, newval, oldval)
+
 /* Store NEWVALUE in *MEM and return the old value.  */
-/* On s390, the atomic_exchange_acq is different from generic implementation,
-   because the generic one does not use the condition-code of cs-instruction
-   to determine if looping is needed. Instead it saves the old-value and
-   compares it against old-value returned by cs-instruction.  */
-#ifdef __s390x__
-# define atomic_exchange_acq(mem, newvalue)				\
-  ({ __typeof (mem) __atg5_memp = (mem);				\
-    __typeof (*(mem)) __atg5_oldval = *__atg5_memp;			\
-    __typeof (*(mem)) __atg5_value = (newvalue);			\
-    if (sizeof (*mem) == 4)						\
-      __asm__ __volatile__ ("0: cs %0,%2,%1\n"				\
-			    "   jl 0b"					\
-			    : "+d" (__atg5_oldval), "=Q" (*__atg5_memp)	\
-			    : "d" (__atg5_value), "m" (*__atg5_memp)	\
-			    : "cc", "memory" );				\
-     else if (sizeof (*mem) == 8)					\
-       __asm__ __volatile__ ("0: csg %0,%2,%1\n"			\
-			     "   jl 0b"					\
-			     : "+d" ( __atg5_oldval), "=Q" (*__atg5_memp) \
-			     : "d" ((long) __atg5_value), "m" (*__atg5_memp) \
-			     : "cc", "memory" );			\
-     else								\
-       abort ();							\
-     __atg5_oldval; })
-#else
-# define atomic_exchange_acq(mem, newvalue)				\
-  ({ __typeof (mem) __atg5_memp = (mem);				\
-    __typeof (*(mem)) __atg5_oldval = *__atg5_memp;			\
-    __typeof (*(mem)) __atg5_value = (newvalue);			\
-    if (sizeof (*mem) == 4)						\
-      __asm__ __volatile__ ("0: cs %0,%2,%1\n"				\
-			    "   jl 0b"					\
-			    : "+d" (__atg5_oldval), "=Q" (*__atg5_memp)	\
-			    : "d" (__atg5_value), "m" (*__atg5_memp)	\
-			    : "cc", "memory" );				\
-    else								\
-      abort ();								\
-    __atg5_oldval; })
-#endif
+#define atomic_exchange_acq(mem, newvalue)				\
+  ({ __atomic_check_size((mem));					\
+    __atomic_exchange_n (mem, newvalue, __ATOMIC_ACQUIRE); })
+#define atomic_exchange_rel(mem, newvalue)				\
+  ({ __atomic_check_size((mem));					\
+    __atomic_exchange_n (mem, newvalue, __ATOMIC_RELEASE); })
+
+/* Add VALUE to *MEM and return the old value of *MEM.  */
+/* The gcc builtin uses load-and-add instruction on z196 zarch and higher cpus
+   instead of a loop with compare-and-swap instruction.  */
+# define atomic_exchange_and_add_acq(mem, operand)			\
+  ({ __atomic_check_size((mem));					\
+  __atomic_fetch_add ((mem), (operand), __ATOMIC_ACQUIRE); })
+# define atomic_exchange_and_add_rel(mem, operand)			\
+  ({ __atomic_check_size((mem));					\
+  __atomic_fetch_add ((mem), (operand), __ATOMIC_RELEASE); })
+#define catomic_exchange_and_add(mem, value)	\
+  atomic_exchange_and_add (mem, value)
+
+/* Atomically *mem |= mask and return the old value of *mem.  */
+/* The gcc builtin uses load-and-or instruction on z196 zarch and higher cpus
+   instead of a loop with compare-and-swap instruction.  */
+#define atomic_or_val(mem, operand)					\
+  ({ __atomic_check_size((mem));					\
+  __atomic_fetch_or ((mem), (operand), __ATOMIC_ACQUIRE); })
+/* Atomically *mem |= mask.  */
+#define atomic_or(mem, mask)			\
+  do {						\
+    atomic_or_val (mem, mask);			\
+  } while (0)
+#define catomic_or(mem, mask)			\
+  atomic_or (mem, mask)
+
+/* Atomically *mem |= 1 << bit and return true if the bit was set in old value
+   of *mem.  */
+/* The load-and-or instruction is used on z196 zarch and higher cpus
+   instead of a loop with compare-and-swap instruction.  */
+#define atomic_bit_test_set(mem, bit)					\
+  ({ __typeof (*(mem)) __atg14_old;					\
+    __typeof (mem) __atg14_memp = (mem);				\
+    __typeof (*(mem)) __atg14_mask = ((__typeof (*(mem))) 1 << (bit));	\
+    __atg14_old = atomic_or_val (__atg14_memp, __atg14_mask);		\
+    __atg14_old & __atg14_mask; })
+
+/* Atomically *mem &= mask and return the old value of *mem.  */
+/* The gcc builtin uses load-and-and instruction on z196 zarch and higher cpus
+   instead of a loop with compare-and-swap instruction.  */
+#define atomic_and_val(mem, operand)					\
+  ({ __atomic_check_size((mem));					\
+  __atomic_fetch_and ((mem), (operand), __ATOMIC_ACQUIRE); })
+/* Atomically *mem &= mask.  */
+#define atomic_and(mem, mask)			\
+  do {						\
+    atomic_and_val (mem, mask);			\
+  } while (0)
+#define catomic_and(mem, mask)			\
+  atomic_and(mem, mask)

Torvald Riegel Feb. 28, 2017, 7:33 a.m. | #4
On Mon, 2017-02-27 at 12:36 +0100, Stefan Liebler wrote:
> This patch activates c11 atomic builtins by defining

> USE_ATOMIC_COMPILER_BUILTINS to 1.

> Note:

> E.g. in nptl/pthread_key_delete.c if compiled with GCCs 6 and before,

> an extra stack-frame is generated and the old value is stored on stack

> before cs instruction but it never loads this value from stack.

> An unreleased GCC 7 omit those stack operations.

> 

> E.g. in nptl/pthread_once.c the condition code of cs instruction is

> evaluated by a sequence of ipm, sra, compare and jump instructions

> instead of one conditional jump instruction.

> This also occurs with an unreleased GCC 7.

> 

> These shortcomings does not really hurt.  Nevertheless, the gcc guys are

> investigating those ones and plan to fix them before GCC 7 release.

> 

> The atomic_fetch_abc_def c11 builtins are now using load-and-abc

> instructions on z196 zarch and higher cpus instead of a loop

> with compare-and-swap instruction.

> 

> Some of the non-c11 atomic macros from include/atomic.h are now

> implemented with help of the c11 atomic builtins.

> The other non-c11 atomic macros are using the macros defined here.

> 

> Optimizations like using load-and-and for exchanging memory to zero

> will be done by GCC in future.

> 

> ChangeLog:

> 

> 	* sysdeps/s390/atomic-machine.h

> 	(USE_ATOMIC_COMPILER_BUILTINS): Define to 1.

> 	(__arch_compare_and_exchange_val_8_acq,

> 	__arch_compare_and_exchange_val_16_acq,

> 	__arch_compare_and_exchange_val_32_acq,

> 	__arch_compare_and_exchange_val_64_acq):

> 	Delete macro.

> 	(atomic_compare_and_exchange_val_acq,

> 	atomic_compare_and_exchange_val_rel,

> 	atomic_compare_and_exchange_bool_acq,

> 	catomic_compare_and_exchange_bool_acq,

> 	atomic_exchange_acq, atomic_exchange_rel,

> 	atomic_exchange_and_add_acq,

> 	atomic_exchange_and_add_rel,

> 	catomic_exchange_and_add, atomic_or_val,

> 	atomic_or, catomic_or, atomic_bit_test_set,

> 	atomic_and_val, atomic_and, catomic_and):

> 	Define macros with help of c11 atomic builtins.


s/c11/C11/ throughout the patch.
Besides that, this looks good to me.  Thanks.
Stefan Liebler March 6, 2017, 2:42 p.m. | #5
On 02/28/2017 08:33 AM, Torvald Riegel wrote:
> On Mon, 2017-02-27 at 12:36 +0100, Stefan Liebler wrote:

>> This patch activates c11 atomic builtins by defining

>> USE_ATOMIC_COMPILER_BUILTINS to 1.

>> Note:

>> E.g. in nptl/pthread_key_delete.c if compiled with GCCs 6 and before,

>> an extra stack-frame is generated and the old value is stored on stack

>> before cs instruction but it never loads this value from stack.

>> An unreleased GCC 7 omit those stack operations.

>>

>> E.g. in nptl/pthread_once.c the condition code of cs instruction is

>> evaluated by a sequence of ipm, sra, compare and jump instructions

>> instead of one conditional jump instruction.

>> This also occurs with an unreleased GCC 7.

>>

>> These shortcomings does not really hurt.  Nevertheless, the gcc guys are

>> investigating those ones and plan to fix them before GCC 7 release.

>>

>> The atomic_fetch_abc_def c11 builtins are now using load-and-abc

>> instructions on z196 zarch and higher cpus instead of a loop

>> with compare-and-swap instruction.

>>

>> Some of the non-c11 atomic macros from include/atomic.h are now

>> implemented with help of the c11 atomic builtins.

>> The other non-c11 atomic macros are using the macros defined here.

>>

>> Optimizations like using load-and-and for exchanging memory to zero

>> will be done by GCC in future.

>>

>> ChangeLog:

>>

>> 	* sysdeps/s390/atomic-machine.h

>> 	(USE_ATOMIC_COMPILER_BUILTINS): Define to 1.

>> 	(__arch_compare_and_exchange_val_8_acq,

>> 	__arch_compare_and_exchange_val_16_acq,

>> 	__arch_compare_and_exchange_val_32_acq,

>> 	__arch_compare_and_exchange_val_64_acq):

>> 	Delete macro.

>> 	(atomic_compare_and_exchange_val_acq,

>> 	atomic_compare_and_exchange_val_rel,

>> 	atomic_compare_and_exchange_bool_acq,

>> 	catomic_compare_and_exchange_bool_acq,

>> 	atomic_exchange_acq, atomic_exchange_rel,

>> 	atomic_exchange_and_add_acq,

>> 	atomic_exchange_and_add_rel,

>> 	catomic_exchange_and_add, atomic_or_val,

>> 	atomic_or, catomic_or, atomic_bit_test_set,

>> 	atomic_and_val, atomic_and, catomic_and):

>> 	Define macros with help of c11 atomic builtins.

>

> s/c11/C11/ throughout the patch.

> Besides that, this looks good to me.  Thanks.

>

Thanks for review.
I've changed c11 to C11 and committed this patch.
Bye.
Stefan

Patch hide | download patch | download mbox

commit 587b15ad5de619a66d647553310c9da79da57a06
Author: Stefan Liebler <stli@linux.vnet.ibm.com>
Date:   Fri Dec 16 17:53:50 2016 +0100

    S390: Optimize atomic macros.
    
    The atomic_compare_and_exchange_val_acq macro is now implemented with
    gcc __sync_val_compare_and_swap instead of an inline assembly with
    compare-and-swap instruction.
    The memory is compared against expected OLDVAL before using compare-and-swap
    instruction in case of OLDVAL is constant at compile time.  This is used in
    various locking code.  If the lock is already aquired, another cpu has not to
    exclusively lock the memory.  If OLDVAL is not constant the compare-and-swap
    instruction is used directly as the usages of this macro usually load the
    current value in front of this macro.
    
    The same applies to atomic_compare_and_exchange_bool_acq which wasn't
    defined before.  Now it is implemented with gcc __sync_bool_compare_and_swap.
    If the macro is used as condition in an if/while expression, the condition
    code is used to e.g. jump directly to another code sequence.  Before this
    change, the old value returned by compare-and-swap instruction was compared
    with given OLDVAL to determine if e.g. a jump is needed.
    
    The atomic_exchange_acq macro is now using the load-and-and instruction for a
    constant zero value instead of a compare-and-swap loop.  This instruction is
    available on a z196 zarch and higher cpus.  This is e.g. used in unlocking code.
    
    The newly defined atomic_exchange_and_add macro is implemented with gcc
    builtin __sync_fetch_and_add which uses load-and-add instruction on z196 zarch
    and higher cpus instead of a loop with compare-and-swap instruction.
    The same applies to atomic_or_val, atomic_and_val, ... macros, which use
    the appropiate z196 instruction.
    
    ChangeLog:
    
    	* sysdeps/s390/atomic-machine.h
    	(__ATOMIC_MACROS_HAVE_Z196_ZARCH_INSN): New define.
    	(atomic_compare_and_exchange_val_acq):
    	Use __sync_val_compare_and_swap and first compare with non-atomic
    	instruction in case of OLDVAL is constant.
    	(atomic_compare_and_exchange_bool_acq): New define.
    	(atomic_exchange_acq): Use load-and-and instruction for constant
    	zero values, if available.
    	(atomic_exchange_and_add, catomic_exchange_and_add, atomic_or_val,
    	atomic_or, catomic_or, atomic_bit_test_set, atomic_and_val,
    	atomic_and, catomic_and): New define.

diff --git a/sysdeps/s390/atomic-machine.h b/sysdeps/s390/atomic-machine.h
index 4ba4107..e6956ff 100644
--- a/sysdeps/s390/atomic-machine.h
+++ b/sysdeps/s390/atomic-machine.h
@@ -45,76 +45,163 @@  typedef uintmax_t uatomic_max_t;
 
 #define USE_ATOMIC_COMPILER_BUILTINS 0
 
-
-#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
-  (abort (), (__typeof (*mem)) 0)
-
-#define __arch_compare_and_exchange_val_16_acq(mem, newval, oldval) \
-  (abort (), (__typeof (*mem)) 0)
-
-#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
-  ({ __typeof (mem) __archmem = (mem);					      \
-     __typeof (*mem) __archold = (oldval);				      \
-     __asm__ __volatile__ ("cs %0,%2,%1"				      \
-			   : "+d" (__archold), "=Q" (*__archmem)	      \
-			   : "d" (newval), "m" (*__archmem) : "cc", "memory" );	\
-     __archold; })
-
 #ifdef __s390x__
 # define __HAVE_64B_ATOMICS 1
-# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
-  ({ __typeof (mem) __archmem = (mem);					      \
-     __typeof (*mem) __archold = (oldval);				      \
-     __asm__ __volatile__ ("csg %0,%2,%1"				      \
-			   : "+d" (__archold), "=Q" (*__archmem)	      \
-			   : "d" ((long) (newval)), "m" (*__archmem) : "cc", "memory" ); \
-     __archold; })
 #else
 # define __HAVE_64B_ATOMICS 0
-/* For 31 bit we do not really need 64-bit compare-and-exchange. We can
-   implement them by use of the csd instruction. The straightforward
-   implementation causes warnings so we skip the definition for now.  */
-# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
-  (abort (), (__typeof (*mem)) 0)
 #endif
 
+#ifdef HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT
+# define __ATOMIC_MACROS_HAVE_Z196_ZARCH_INSN 1
+#else
+# define __ATOMIC_MACROS_HAVE_Z196_ZARCH_INSN 0
+#endif
+
+/* Atomically store NEWVAL in *MEM if *MEM is equal to OLDVAL.
+   Return the old *MEM value.  */
+/* Compare *MEM against expected OLDVAL before using compare-and-swap
+   instruction in case of OLDVAL is constant.  This is used in various
+   locking code.  If the lock is already aquired another cpu has not to
+   exclusively lock the memory.  */
+#define atomic_compare_and_exchange_val_acq(mem, newval, oldval)	\
+  ({ __asm__ __volatile__ ("" ::: "memory");				\
+    __typeof (*(mem)) __atg1_ret;					\
+    if (!__builtin_constant_p (oldval)					\
+	|| __builtin_expect ((__atg1_ret = *(mem))			\
+			     == (oldval), 1))				\
+      __atg1_ret = __sync_val_compare_and_swap ((mem), (oldval),	\
+						(newval));		\
+    else								\
+      __asm__ __volatile__ ("" ::: "memory");				\
+    __atg1_ret; })
+
+/* Atomically store NEWVAL in *MEM if *MEM is equal to OLDVAL.
+   Return zero if *MEM was changed or non-zero if no exchange happened.  */
+/* Same as with atomic_compare_and_exchange_val_acq,  constant OLDVALs are
+   compared before using compare-and-swap instruction.  As this macro is
+   normally used in conjunction with if or while, gcc emits a conditional-
+   branch instruction to use the condition-code of compare-and-swap instruction
+   instead of comparing the old value.  */
+#define atomic_compare_and_exchange_bool_acq(mem, newval, oldval)	\
+  ({ __asm__ __volatile__ ("" ::: "memory");				\
+    int __atg3_ret = 1;							\
+    if (!__builtin_constant_p (oldval)					\
+	|| __builtin_expect (*(mem) == (oldval), 1))			\
+      __atg3_ret = !__sync_bool_compare_and_swap ((mem), (oldval),	\
+						  (newval));		\
+    else								\
+      __asm__ __volatile__ ("" ::: "memory");				\
+    __atg3_ret; })
+
 /* Store NEWVALUE in *MEM and return the old value.  */
 /* On s390, the atomic_exchange_acq is different from generic implementation,
    because the generic one does not use the condition-code of cs-instruction
-   to determine if looping is needed. Instead it saves the old-value and
-   compares it against old-value returned by cs-instruction.  */
+   to determine if looping is needed.  Instead it saves the old-value and
+   compares it against old-value returned by cs-instruction.
+   Setting a constant zero can be done with load-and-and instruction which
+   is available on a z196 zarch and higher cpus.  This is used in unlocking
+   code.  */
 #ifdef __s390x__
 # define atomic_exchange_acq(mem, newvalue)				\
-  ({ __typeof (mem) __atg5_memp = (mem);				\
-    __typeof (*(mem)) __atg5_oldval = *__atg5_memp;			\
-    __typeof (*(mem)) __atg5_value = (newvalue);			\
-    if (sizeof (*mem) == 4)						\
-      __asm__ __volatile__ ("0: cs %0,%2,%1\n"				\
-			    "   jl 0b"					\
-			    : "+d" (__atg5_oldval), "=Q" (*__atg5_memp)	\
-			    : "d" (__atg5_value), "m" (*__atg5_memp)	\
-			    : "cc", "memory" );				\
-     else if (sizeof (*mem) == 8)					\
-       __asm__ __volatile__ ("0: csg %0,%2,%1\n"			\
-			     "   jl 0b"					\
-			     : "+d" ( __atg5_oldval), "=Q" (*__atg5_memp) \
-			     : "d" ((long) __atg5_value), "m" (*__atg5_memp) \
-			     : "cc", "memory" );			\
-     else								\
-       abort ();							\
+  ({ __typeof (*(mem)) __atg5_oldval;					\
+    if (__ATOMIC_MACROS_HAVE_Z196_ZARCH_INSN != 0			\
+	&& __builtin_constant_p (newvalue) && (newvalue) == 0)		\
+      {									\
+	__atg5_oldval = __sync_fetch_and_and (mem, 0);			\
+      }									\
+    else								\
+      {									\
+	__typeof (mem) __atg5_memp = (mem);				\
+	__atg5_oldval = *__atg5_memp;					\
+	__typeof (*(mem)) __atg5_value = (newvalue);			\
+	if (sizeof (*(mem)) == 4)					\
+	  __asm__ __volatile__ ("0: cs %0,%2,%1\n"			\
+				"   jl 0b"				\
+				: "+d" (__atg5_oldval),			\
+				  "=Q" (*__atg5_memp)			\
+				: "d" (__atg5_value),			\
+				  "m" (*__atg5_memp)			\
+				: "cc", "memory" );			\
+	else if (sizeof (*(mem)) == 8)					\
+	  __asm__ __volatile__ ("0: csg %0,%2,%1\n"			\
+				"   jl 0b"				\
+				: "+d" ( __atg5_oldval),		\
+				  "=Q" (*__atg5_memp)			\
+				: "d" ((long) __atg5_value),		\
+				  "m" (*__atg5_memp)			\
+				: "cc", "memory" );			\
+	else								\
+	  abort ();							\
+      }									\
      __atg5_oldval; })
 #else
 # define atomic_exchange_acq(mem, newvalue)				\
-  ({ __typeof (mem) __atg5_memp = (mem);				\
-    __typeof (*(mem)) __atg5_oldval = *__atg5_memp;			\
-    __typeof (*(mem)) __atg5_value = (newvalue);			\
-    if (sizeof (*mem) == 4)						\
-      __asm__ __volatile__ ("0: cs %0,%2,%1\n"				\
-			    "   jl 0b"					\
-			    : "+d" (__atg5_oldval), "=Q" (*__atg5_memp)	\
-			    : "d" (__atg5_value), "m" (*__atg5_memp)	\
-			    : "cc", "memory" );				\
+  ({ __typeof (*(mem)) __atg5_oldval;					\
+    if (__ATOMIC_MACROS_HAVE_Z196_ZARCH_INSN != 0			\
+	&& __builtin_constant_p (newvalue) && (newvalue) == 0)		\
+      {									\
+	__atg5_oldval = __sync_fetch_and_and (mem, 0);			\
+      }									\
     else								\
-      abort ();								\
+      {									\
+	__typeof (mem) __atg5_memp = (mem);				\
+	__atg5_oldval = *__atg5_memp;					\
+	__typeof (*(mem)) __atg5_value = (newvalue);			\
+	if (sizeof (*(mem)) == 4)					\
+	  __asm__ __volatile__ ("0: cs %0,%2,%1\n"			\
+				"   jl 0b"				\
+				: "+d" (__atg5_oldval),			\
+				  "=Q" (*__atg5_memp)			\
+				: "d" (__atg5_value),			\
+				  "m" (*__atg5_memp)			\
+				: "cc", "memory" );			\
+	else								\
+	  abort ();							\
+      }									\
     __atg5_oldval; })
 #endif
+
+/* Add VALUE to *MEM and return the old value of *MEM.  */
+/* The gcc builtin uses load-and-add instruction on z196 zarch and higher cpus
+   instead of a loop with compare-and-swap instruction.  */
+#define atomic_exchange_and_add(mem, value)	\
+  __sync_fetch_and_add (mem, value)
+#define catomic_exchange_and_add(mem, value)	\
+  atomic_exchange_and_add (mem, value)
+
+/* Atomically *mem |= mask and return the old value of *mem.  */
+/* The gcc builtin uses load-and-or instruction on z196 zarch and higher cpus
+   instead of a loop with compare-and-swap instruction.  */
+#define atomic_or_val(mem, mask)		\
+  __sync_fetch_and_or (mem, mask)
+/* Atomically *mem |= mask.  */
+#define atomic_or(mem, mask)			\
+  do {						\
+    atomic_or_val (mem, mask);			\
+  } while (0)
+#define catomic_or(mem, mask)			\
+  atomic_or (mem, mask)
+
+/* Atomically *mem |= 1 << bit and return true if the bit was set in old value
+   of *mem.  */
+/* The load-and-or instruction is used on z196 zarch and higher cpus
+   instead of a loop with compare-and-swap instruction.  */
+#define atomic_bit_test_set(mem, bit)					\
+  ({ __typeof (*(mem)) __atg14_old;					\
+    __typeof (mem) __atg14_memp = (mem);				\
+    __typeof (*(mem)) __atg14_mask = ((__typeof (*(mem))) 1 << (bit));	\
+    __atg14_old = atomic_or_val (__atg14_memp, __atg14_mask);		\
+    __atg14_old & __atg14_mask; })
+
+/* Atomically *mem &= mask and return the old value of *mem.  */
+/* The gcc builtin uses load-and-and instruction on z196 zarch and higher cpus
+   instead of a loop with compare-and-swap instruction.  */
+#define atomic_and_val(mem, mask)		\
+  __sync_fetch_and_and (mem, mask)
+/* Atomically *mem &= mask.  */
+#define atomic_and(mem, mask)			\
+  do {						\
+    atomic_and_val (mem, mask);			\
+  } while (0)
+#define catomic_and(mem, mask)			\
+  atomic_and(mem, mask)