diff mbox

USB: EXYNOS: Incorporate EHCI review comments

Message ID 1337598483-16839-1-git-send-email-rajeshwari.s@samsung.com
State Accepted
Commit 7590d3cece3a4152bc60d6f1ca84b09f7abbf3cf
Headers show

Commit Message

Rajeshwari Shinde May 21, 2012, 11:08 a.m. UTC 
This patch incorates the review comments given by Minkyu Kang for 
EHCI support on EXYNOS

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
---
 arch/arm/include/asm/arch-exynos/cpu.h      |    3 +
 arch/arm/include/asm/arch-exynos/ehci-s5p.h |   66 ----------------
 arch/arm/include/asm/arch-exynos/ehci.h     |   66 ++++++++++++++++
 drivers/usb/host/Makefile                   |    2 +-
 drivers/usb/host/ehci-exynos.c              |  110 +++++++++++++++++++++++++++
 drivers/usb/host/ehci-s5p.c                 |  110 ---------------------------
 6 files changed, 180 insertions(+), 177 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-exynos/ehci-s5p.h
 create mode 100644 arch/arm/include/asm/arch-exynos/ehci.h
 create mode 100644 drivers/usb/host/ehci-exynos.c
 delete mode 100644 drivers/usb/host/ehci-s5p.c

Comments

Marek Vasut May 22, 2012, 1:19 a.m. UTC | #1 
Dear Rajeshwari Shinde,

> This patch incorates the review comments given by Minkyu Kang for
> EHCI support on EXYNOS
> 
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>

Perfect, applied and applied those 6 patches that were dangling. Now, I pushed 
out new usb/master branch, can you please verify if it's all you need from me 
before I submit another pull RQ?

Sorry I wasn't really a textbook example of a maintainer, I hope we I'll still 
see more code from you eventually.

Thank you very much for the work you put into these patches and all the 
additional (unnecessary) hassle!

> ---
>  arch/arm/include/asm/arch-exynos/cpu.h      |    3 +
>  arch/arm/include/asm/arch-exynos/ehci-s5p.h |   66 ----------------
>  arch/arm/include/asm/arch-exynos/ehci.h     |   66 ++++++++++++++++
>  drivers/usb/host/Makefile                   |    2 +-
>  drivers/usb/host/ehci-exynos.c              |  110
> +++++++++++++++++++++++++++ drivers/usb/host/ehci-s5p.c                 | 
> 110 --------------------------- 6 files changed, 180 insertions(+), 177
> deletions(-)
>  delete mode 100644 arch/arm/include/asm/arch-exynos/ehci-s5p.h
>  create mode 100644 arch/arm/include/asm/arch-exynos/ehci.h
>  create mode 100644 drivers/usb/host/ehci-exynos.c
>  delete mode 100644 drivers/usb/host/ehci-s5p.c
> 
> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
> b/arch/arm/include/asm/arch-exynos/cpu.h index ac4ddc7..85d421d 100644
> --- a/arch/arm/include/asm/arch-exynos/cpu.h
> +++ b/arch/arm/include/asm/arch-exynos/cpu.h
> @@ -45,6 +45,7 @@
>  #define EXYNOS4_USBOTG_BASE		0x12480000
>  #define EXYNOS4_MMC_BASE		0x12510000
>  #define EXYNOS4_SROMC_BASE		0x12570000
> +#define EXYNOS4_USB_HOST_EHCI_BASE	0x12580000
>  #define EXYNOS4_USBPHY_BASE		0x125B0000
>  #define EXYNOS4_UART_BASE		0x13800000
>  #define EXYNOS4_ADC_BASE		0x13910000
> @@ -68,6 +69,7 @@
>  #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
>  #define EXYNOS5_GPIO_PART1_BASE		0x11400000
>  #define EXYNOS5_MIPI_DSIM_BASE		0x11D00000
> +#define EXYNOS5_USB_HOST_EHCI_BASE	0x12110000
>  #define EXYNOS5_MMC_BASE		0x12200000
>  #define EXYNOS5_SROMC_BASE		0x12250000
>  #define EXYNOS5_USBOTG_BASE		0x12480000
> @@ -145,6 +147,7 @@ SAMSUNG_BASE(swreset, SWRESET)
>  SAMSUNG_BASE(timer, PWMTIMER_BASE)
>  SAMSUNG_BASE(uart, UART_BASE)
>  SAMSUNG_BASE(usb_phy, USBPHY_BASE)
> +SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
>  SAMSUNG_BASE(usb_otg, USBOTG_BASE)
>  SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
>  SAMSUNG_BASE(power, POWER_BASE)
> diff --git a/arch/arm/include/asm/arch-exynos/ehci-s5p.h
> b/arch/arm/include/asm/arch-exynos/ehci-s5p.h deleted file mode 100644
> index 68feb85..0000000
> --- a/arch/arm/include/asm/arch-exynos/ehci-s5p.h
> +++ /dev/null
> @@ -1,66 +0,0 @@
> -/*
> - * SAMSUNG S5P USB HOST EHCI Controller
> - *
> - * Copyright (C) 2012 Samsung Electronics Co.Ltd
> - *	Vivek Gautam <gautam.vivek@samsung.com>
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> - * MA 02110-1301 USA
> - */
> -
> -#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
> -#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
> -
> -#define CLK_24MHZ		5
> -
> -#define HOST_CTRL0_PHYSWRSTALL			(1 << 31)
> -#define HOST_CTRL0_COMMONON_N			(1 << 9)
> -#define HOST_CTRL0_SIDDQ			(1 << 6)
> -#define HOST_CTRL0_FORCESLEEP			(1 << 5)
> -#define HOST_CTRL0_FORCESUSPEND			(1 << 4)
> -#define HOST_CTRL0_WORDINTERFACE		(1 << 3)
> -#define HOST_CTRL0_UTMISWRST			(1 << 2)
> -#define HOST_CTRL0_LINKSWRST			(1 << 1)
> -#define HOST_CTRL0_PHYSWRST			(1 << 0)
> -
> -#define HOST_CTRL0_FSEL_MASK			(7 << 16)
> -
> -#define EHCICTRL_ENAINCRXALIGN			(1 << 29)
> -#define EHCICTRL_ENAINCR4			(1 << 28)
> -#define EHCICTRL_ENAINCR8			(1 << 27)
> -#define EHCICTRL_ENAINCR16			(1 << 26)
> -
> -/* Register map for PHY control */
> -struct s5p_usb_phy {
> -	unsigned int usbphyctrl0;
> -	unsigned int usbphytune0;
> -	unsigned int reserved1[2];
> -	unsigned int hsicphyctrl1;
> -	unsigned int hsicphytune1;
> -	unsigned int reserved2[2];
> -	unsigned int hsicphyctrl2;
> -	unsigned int hsicphytune2;
> -	unsigned int reserved3[2];
> -	unsigned int ehcictrl;
> -	unsigned int ohcictrl;
> -	unsigned int usbotgsys;
> -	unsigned int reserved4;
> -	unsigned int usbotgtune;
> -};
> -
> -/* Switch on the VBUS power. */
> -int board_usb_vbus_init(void);
> -
> -#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */
> diff --git a/arch/arm/include/asm/arch-exynos/ehci.h
> b/arch/arm/include/asm/arch-exynos/ehci.h new file mode 100644
> index 0000000..8aeff8a
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-exynos/ehci.h
> @@ -0,0 +1,66 @@
> +/*
> + * SAMSUNG EXYNOS USB HOST EHCI Controller
> + *
> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
> + *	Vivek Gautam <gautam.vivek@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef __ASM_ARM_ARCH_EHCI_H__
> +#define __ASM_ARM_ARCH_EHCI_H__
> +
> +#define CLK_24MHZ		5
> +
> +#define HOST_CTRL0_PHYSWRSTALL			(1 << 31)
> +#define HOST_CTRL0_COMMONON_N			(1 << 9)
> +#define HOST_CTRL0_SIDDQ			(1 << 6)
> +#define HOST_CTRL0_FORCESLEEP			(1 << 5)
> +#define HOST_CTRL0_FORCESUSPEND			(1 << 4)
> +#define HOST_CTRL0_WORDINTERFACE		(1 << 3)
> +#define HOST_CTRL0_UTMISWRST			(1 << 2)
> +#define HOST_CTRL0_LINKSWRST			(1 << 1)
> +#define HOST_CTRL0_PHYSWRST			(1 << 0)
> +
> +#define HOST_CTRL0_FSEL_MASK			(7 << 16)
> +
> +#define EHCICTRL_ENAINCRXALIGN			(1 << 29)
> +#define EHCICTRL_ENAINCR4			(1 << 28)
> +#define EHCICTRL_ENAINCR8			(1 << 27)
> +#define EHCICTRL_ENAINCR16			(1 << 26)
> +
> +/* Register map for PHY control */
> +struct exynos_usb_phy {
> +	unsigned int usbphyctrl0;
> +	unsigned int usbphytune0;
> +	unsigned int reserved1[2];
> +	unsigned int hsicphyctrl1;
> +	unsigned int hsicphytune1;
> +	unsigned int reserved2[2];
> +	unsigned int hsicphyctrl2;
> +	unsigned int hsicphytune2;
> +	unsigned int reserved3[2];
> +	unsigned int ehcictrl;
> +	unsigned int ohcictrl;
> +	unsigned int usbotgsys;
> +	unsigned int reserved4;
> +	unsigned int usbotgtune;
> +};
> +
> +/* Switch on the VBUS power. */
> +int board_usb_vbus_init(void);
> +
> +#endif /* __ASM_ARM_ARCH_EHCI_H__ */
> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
> index 59c3e57..645bb58 100644
> --- a/drivers/usb/host/Makefile
> +++ b/drivers/usb/host/Makefile
> @@ -41,6 +41,7 @@ COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
>  else
>  COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
>  endif
> +COBJS-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
>  COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
>  COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
>  COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
> @@ -50,7 +51,6 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
>  COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
>  COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
>  COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
> -COBJS-$(CONFIG_USB_EHCI_S5P) += ehci-s5p.o
>  COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
>  COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
> 
> diff --git a/drivers/usb/host/ehci-exynos.c
> b/drivers/usb/host/ehci-exynos.c new file mode 100644
> index 0000000..3830c43
> --- /dev/null
> +++ b/drivers/usb/host/ehci-exynos.c
> @@ -0,0 +1,110 @@
> +/*
> + * SAMSUNG EXYNOS USB HOST EHCI Controller
> + *
> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
> + *	Vivek Gautam <gautam.vivek@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <usb.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/ehci.h>
> +#include "ehci.h"
> +#include "ehci-core.h"
> +
> +/* Setup the EHCI host controller. */
> +static void setup_usb_phy(struct exynos_usb_phy *usb)
> +{
> +	clrbits_le32(&usb->usbphyctrl0,
> +			HOST_CTRL0_FSEL_MASK |
> +			HOST_CTRL0_COMMONON_N |
> +			/* HOST Phy setting */
> +			HOST_CTRL0_PHYSWRST |
> +			HOST_CTRL0_PHYSWRSTALL |
> +			HOST_CTRL0_SIDDQ |
> +			HOST_CTRL0_FORCESUSPEND |
> +			HOST_CTRL0_FORCESLEEP);
> +
> +	setbits_le32(&usb->usbphyctrl0,
> +			/* Setting up the ref freq */
> +			(CLK_24MHZ << 16) |
> +			/* HOST Phy setting */
> +			HOST_CTRL0_LINKSWRST |
> +			HOST_CTRL0_UTMISWRST);
> +	udelay(10);
> +	clrbits_le32(&usb->usbphyctrl0,
> +			HOST_CTRL0_LINKSWRST |
> +			HOST_CTRL0_UTMISWRST);
> +	udelay(20);
> +
> +	/* EHCI Ctrl setting */
> +	setbits_le32(&usb->ehcictrl,
> +			EHCICTRL_ENAINCRXALIGN |
> +			EHCICTRL_ENAINCR4 |
> +			EHCICTRL_ENAINCR8 |
> +			EHCICTRL_ENAINCR16);
> +}
> +
> +/* Reset the EHCI host controller. */
> +static void reset_usb_phy(struct exynos_usb_phy *usb)
> +{
> +	/* HOST_PHY reset */
> +	setbits_le32(&usb->usbphyctrl0,
> +			HOST_CTRL0_PHYSWRST |
> +			HOST_CTRL0_PHYSWRSTALL |
> +			HOST_CTRL0_SIDDQ |
> +			HOST_CTRL0_FORCESUSPEND |
> +			HOST_CTRL0_FORCESLEEP);
> +}
> +
> +/*
> + * EHCI-initialization
> + * Create the appropriate control structures to manage
> + * a new EHCI host controller.
> + */
> +int ehci_hcd_init(void)
> +{
> +	struct exynos_usb_phy *usb;
> +
> +	usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
> +	setup_usb_phy(usb);
> +
> +	hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci();
> +	hcor = (struct ehci_hcor *)((uint32_t) hccr
> +				+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
> +
> +	debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
> +		(uint32_t)hccr, (uint32_t)hcor,
> +		(uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
> +
> +	return 0;
> +}
> +
> +/*
> + * Destroy the appropriate control structures corresponding
> + * the EHCI host controller.
> + */
> +int ehci_hcd_stop()
> +{
> +	struct exynos_usb_phy *usb;
> +
> +	usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
> +	reset_usb_phy(usb);
> +
> +	return 0;
> +}
> diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
> deleted file mode 100644
> index 4dd4ec1..0000000
> --- a/drivers/usb/host/ehci-s5p.c
> +++ /dev/null
> @@ -1,110 +0,0 @@
> -/*
> - * SAMSUNG S5P USB HOST EHCI Controller
> - *
> - * Copyright (C) 2012 Samsung Electronics Co.Ltd
> - *	Vivek Gautam <gautam.vivek@samsung.com>
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * You should have received a copy of the GNU General Public License
> - * along with this program; if not, write to the Free Software
> - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> - * MA 02110-1301 USA
> - */
> -
> -#include <common.h>
> -#include <usb.h>
> -#include <asm/arch/cpu.h>
> -#include <asm/arch/ehci-s5p.h>
> -#include "ehci.h"
> -#include "ehci-core.h"
> -
> -/* Setup the EHCI host controller. */
> -static void setup_usb_phy(struct s5p_usb_phy *usb)
> -{
> -	clrbits_le32(&usb->usbphyctrl0,
> -			HOST_CTRL0_FSEL_MASK |
> -			HOST_CTRL0_COMMONON_N |
> -			/* HOST Phy setting */
> -			HOST_CTRL0_PHYSWRST |
> -			HOST_CTRL0_PHYSWRSTALL |
> -			HOST_CTRL0_SIDDQ |
> -			HOST_CTRL0_FORCESUSPEND |
> -			HOST_CTRL0_FORCESLEEP);
> -
> -	setbits_le32(&usb->usbphyctrl0,
> -			/* Setting up the ref freq */
> -			(CLK_24MHZ << 16) |
> -			/* HOST Phy setting */
> -			HOST_CTRL0_LINKSWRST |
> -			HOST_CTRL0_UTMISWRST);
> -	udelay(10);
> -	clrbits_le32(&usb->usbphyctrl0,
> -			HOST_CTRL0_LINKSWRST |
> -			HOST_CTRL0_UTMISWRST);
> -	udelay(20);
> -
> -	/* EHCI Ctrl setting */
> -	setbits_le32(&usb->ehcictrl,
> -			EHCICTRL_ENAINCRXALIGN |
> -			EHCICTRL_ENAINCR4 |
> -			EHCICTRL_ENAINCR8 |
> -			EHCICTRL_ENAINCR16);
> -}
> -
> -/* Reset the EHCI host controller. */
> -static void reset_usb_phy(struct s5p_usb_phy *usb)
> -{
> -	/* HOST_PHY reset */
> -	setbits_le32(&usb->usbphyctrl0,
> -			HOST_CTRL0_PHYSWRST |
> -			HOST_CTRL0_PHYSWRSTALL |
> -			HOST_CTRL0_SIDDQ |
> -			HOST_CTRL0_FORCESUSPEND |
> -			HOST_CTRL0_FORCESLEEP);
> -}
> -
> -/*
> - * EHCI-initialization
> - * Create the appropriate control structures to manage
> - * a new EHCI host controller.
> - */
> -int ehci_hcd_init(void)
> -{
> -	struct s5p_usb_phy *usb;
> -
> -	usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();
> -	setup_usb_phy(usb);
> -
> -	hccr = (struct ehci_hccr *)(EXYNOS5_USB_HOST_EHCI_BASE);
> -	hcor = (struct ehci_hcor *)((uint32_t) hccr
> -				+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
> -
> -	debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
> -		(uint32_t)hccr, (uint32_t)hcor,
> -		(uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
> -
> -	return 0;
> -}
> -
> -/*
> - * Destroy the appropriate control structures corresponding
> - * the EHCI host controller.
> - */
> -int ehci_hcd_stop()
> -{
> -	struct s5p_usb_phy *usb;
> -
> -	usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();
> -	reset_usb_phy(usb);
> -
> -	return 0;
> -}
Rajeshwari Birje May 22, 2012, 5:10 a.m. UTC | #2 
Hi Marek,

On Tue, May 22, 2012 at 6:49 AM, Marek Vasut <marex@denx.de> wrote:
> Dear Rajeshwari Shinde,
>
>> This patch incorates the review comments given by Minkyu Kang for
>> EHCI support on EXYNOS
>>
>> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
>
> Perfect, applied and applied those 6 patches that were dangling. Now, I pushed
> out new usb/master branch, can you please verify if it's all you need from me
> before I submit another pull RQ?
Verified  all patches there.
> Sorry I wasn't really a textbook example of a maintainer, I hope we I'll still
> see more code from you eventually.
>
> Thank you very much for the work you put into these patches and all the
> additional (unnecessary) hassle!
No problem. Thank you for incorporating them.
>
>> ---
>>  arch/arm/include/asm/arch-exynos/cpu.h      |    3 +
>>  arch/arm/include/asm/arch-exynos/ehci-s5p.h |   66 ----------------
>>  arch/arm/include/asm/arch-exynos/ehci.h     |   66 ++++++++++++++++
>>  drivers/usb/host/Makefile                   |    2 +-
>>  drivers/usb/host/ehci-exynos.c              |  110
>> +++++++++++++++++++++++++++ drivers/usb/host/ehci-s5p.c                 |
>> 110 --------------------------- 6 files changed, 180 insertions(+), 177
>> deletions(-)
>>  delete mode 100644 arch/arm/include/asm/arch-exynos/ehci-s5p.h
>>  create mode 100644 arch/arm/include/asm/arch-exynos/ehci.h
>>  create mode 100644 drivers/usb/host/ehci-exynos.c
>>  delete mode 100644 drivers/usb/host/ehci-s5p.c
>>
>> diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
>> b/arch/arm/include/asm/arch-exynos/cpu.h index ac4ddc7..85d421d 100644
>> --- a/arch/arm/include/asm/arch-exynos/cpu.h
>> +++ b/arch/arm/include/asm/arch-exynos/cpu.h
>> @@ -45,6 +45,7 @@
>>  #define EXYNOS4_USBOTG_BASE          0x12480000
>>  #define EXYNOS4_MMC_BASE             0x12510000
>>  #define EXYNOS4_SROMC_BASE           0x12570000
>> +#define EXYNOS4_USB_HOST_EHCI_BASE   0x12580000
>>  #define EXYNOS4_USBPHY_BASE          0x125B0000
>>  #define EXYNOS4_UART_BASE            0x13800000
>>  #define EXYNOS4_ADC_BASE             0x13910000
>> @@ -68,6 +69,7 @@
>>  #define EXYNOS5_DMC_CTRL_BASE                0x10DD0000
>>  #define EXYNOS5_GPIO_PART1_BASE              0x11400000
>>  #define EXYNOS5_MIPI_DSIM_BASE               0x11D00000
>> +#define EXYNOS5_USB_HOST_EHCI_BASE   0x12110000
>>  #define EXYNOS5_MMC_BASE             0x12200000
>>  #define EXYNOS5_SROMC_BASE           0x12250000
>>  #define EXYNOS5_USBOTG_BASE          0x12480000
>> @@ -145,6 +147,7 @@ SAMSUNG_BASE(swreset, SWRESET)
>>  SAMSUNG_BASE(timer, PWMTIMER_BASE)
>>  SAMSUNG_BASE(uart, UART_BASE)
>>  SAMSUNG_BASE(usb_phy, USBPHY_BASE)
>> +SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
>>  SAMSUNG_BASE(usb_otg, USBOTG_BASE)
>>  SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
>>  SAMSUNG_BASE(power, POWER_BASE)
>> diff --git a/arch/arm/include/asm/arch-exynos/ehci-s5p.h
>> b/arch/arm/include/asm/arch-exynos/ehci-s5p.h deleted file mode 100644
>> index 68feb85..0000000
>> --- a/arch/arm/include/asm/arch-exynos/ehci-s5p.h
>> +++ /dev/null
>> @@ -1,66 +0,0 @@
>> -/*
>> - * SAMSUNG S5P USB HOST EHCI Controller
>> - *
>> - * Copyright (C) 2012 Samsung Electronics Co.Ltd
>> - *   Vivek Gautam <gautam.vivek@samsung.com>
>> - *
>> - * This program is free software; you can redistribute it and/or
>> - * modify it under the terms of the GNU General Public License as
>> - * published by the Free Software Foundation; either version 2 of
>> - * the License, or (at your option) any later version.
>> - *
>> - * This program is distributed in the hope that it will be useful,
>> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> - * GNU General Public License for more details.
>> - *
>> - * You should have received a copy of the GNU General Public License
>> - * along with this program; if not, write to the Free Software
>> - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
>> - * MA 02110-1301 USA
>> - */
>> -
>> -#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
>> -#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
>> -
>> -#define CLK_24MHZ            5
>> -
>> -#define HOST_CTRL0_PHYSWRSTALL                       (1 << 31)
>> -#define HOST_CTRL0_COMMONON_N                        (1 << 9)
>> -#define HOST_CTRL0_SIDDQ                     (1 << 6)
>> -#define HOST_CTRL0_FORCESLEEP                        (1 << 5)
>> -#define HOST_CTRL0_FORCESUSPEND                      (1 << 4)
>> -#define HOST_CTRL0_WORDINTERFACE             (1 << 3)
>> -#define HOST_CTRL0_UTMISWRST                 (1 << 2)
>> -#define HOST_CTRL0_LINKSWRST                 (1 << 1)
>> -#define HOST_CTRL0_PHYSWRST                  (1 << 0)
>> -
>> -#define HOST_CTRL0_FSEL_MASK                 (7 << 16)
>> -
>> -#define EHCICTRL_ENAINCRXALIGN                       (1 << 29)
>> -#define EHCICTRL_ENAINCR4                    (1 << 28)
>> -#define EHCICTRL_ENAINCR8                    (1 << 27)
>> -#define EHCICTRL_ENAINCR16                   (1 << 26)
>> -
>> -/* Register map for PHY control */
>> -struct s5p_usb_phy {
>> -     unsigned int usbphyctrl0;
>> -     unsigned int usbphytune0;
>> -     unsigned int reserved1[2];
>> -     unsigned int hsicphyctrl1;
>> -     unsigned int hsicphytune1;
>> -     unsigned int reserved2[2];
>> -     unsigned int hsicphyctrl2;
>> -     unsigned int hsicphytune2;
>> -     unsigned int reserved3[2];
>> -     unsigned int ehcictrl;
>> -     unsigned int ohcictrl;
>> -     unsigned int usbotgsys;
>> -     unsigned int reserved4;
>> -     unsigned int usbotgtune;
>> -};
>> -
>> -/* Switch on the VBUS power. */
>> -int board_usb_vbus_init(void);
>> -
>> -#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */
>> diff --git a/arch/arm/include/asm/arch-exynos/ehci.h
>> b/arch/arm/include/asm/arch-exynos/ehci.h new file mode 100644
>> index 0000000..8aeff8a
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-exynos/ehci.h
>> @@ -0,0 +1,66 @@
>> +/*
>> + * SAMSUNG EXYNOS USB HOST EHCI Controller
>> + *
>> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
>> + *   Vivek Gautam <gautam.vivek@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
>> + * MA 02110-1301 USA
>> + */
>> +
>> +#ifndef __ASM_ARM_ARCH_EHCI_H__
>> +#define __ASM_ARM_ARCH_EHCI_H__
>> +
>> +#define CLK_24MHZ            5
>> +
>> +#define HOST_CTRL0_PHYSWRSTALL                       (1 << 31)
>> +#define HOST_CTRL0_COMMONON_N                        (1 << 9)
>> +#define HOST_CTRL0_SIDDQ                     (1 << 6)
>> +#define HOST_CTRL0_FORCESLEEP                        (1 << 5)
>> +#define HOST_CTRL0_FORCESUSPEND                      (1 << 4)
>> +#define HOST_CTRL0_WORDINTERFACE             (1 << 3)
>> +#define HOST_CTRL0_UTMISWRST                 (1 << 2)
>> +#define HOST_CTRL0_LINKSWRST                 (1 << 1)
>> +#define HOST_CTRL0_PHYSWRST                  (1 << 0)
>> +
>> +#define HOST_CTRL0_FSEL_MASK                 (7 << 16)
>> +
>> +#define EHCICTRL_ENAINCRXALIGN                       (1 << 29)
>> +#define EHCICTRL_ENAINCR4                    (1 << 28)
>> +#define EHCICTRL_ENAINCR8                    (1 << 27)
>> +#define EHCICTRL_ENAINCR16                   (1 << 26)
>> +
>> +/* Register map for PHY control */
>> +struct exynos_usb_phy {
>> +     unsigned int usbphyctrl0;
>> +     unsigned int usbphytune0;
>> +     unsigned int reserved1[2];
>> +     unsigned int hsicphyctrl1;
>> +     unsigned int hsicphytune1;
>> +     unsigned int reserved2[2];
>> +     unsigned int hsicphyctrl2;
>> +     unsigned int hsicphytune2;
>> +     unsigned int reserved3[2];
>> +     unsigned int ehcictrl;
>> +     unsigned int ohcictrl;
>> +     unsigned int usbotgsys;
>> +     unsigned int reserved4;
>> +     unsigned int usbotgtune;
>> +};
>> +
>> +/* Switch on the VBUS power. */
>> +int board_usb_vbus_init(void);
>> +
>> +#endif /* __ASM_ARM_ARCH_EHCI_H__ */
>> diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
>> index 59c3e57..645bb58 100644
>> --- a/drivers/usb/host/Makefile
>> +++ b/drivers/usb/host/Makefile
>> @@ -41,6 +41,7 @@ COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
>>  else
>>  COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
>>  endif
>> +COBJS-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
>>  COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
>>  COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
>>  COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
>> @@ -50,7 +51,6 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
>>  COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
>>  COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
>>  COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
>> -COBJS-$(CONFIG_USB_EHCI_S5P) += ehci-s5p.o
>>  COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
>>  COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
>>
>> diff --git a/drivers/usb/host/ehci-exynos.c
>> b/drivers/usb/host/ehci-exynos.c new file mode 100644
>> index 0000000..3830c43
>> --- /dev/null
>> +++ b/drivers/usb/host/ehci-exynos.c
>> @@ -0,0 +1,110 @@
>> +/*
>> + * SAMSUNG EXYNOS USB HOST EHCI Controller
>> + *
>> + * Copyright (C) 2012 Samsung Electronics Co.Ltd
>> + *   Vivek Gautam <gautam.vivek@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
>> + * MA 02110-1301 USA
>> + */
>> +
>> +#include <common.h>
>> +#include <usb.h>
>> +#include <asm/arch/cpu.h>
>> +#include <asm/arch/ehci.h>
>> +#include "ehci.h"
>> +#include "ehci-core.h"
>> +
>> +/* Setup the EHCI host controller. */
>> +static void setup_usb_phy(struct exynos_usb_phy *usb)
>> +{
>> +     clrbits_le32(&usb->usbphyctrl0,
>> +                     HOST_CTRL0_FSEL_MASK |
>> +                     HOST_CTRL0_COMMONON_N |
>> +                     /* HOST Phy setting */
>> +                     HOST_CTRL0_PHYSWRST |
>> +                     HOST_CTRL0_PHYSWRSTALL |
>> +                     HOST_CTRL0_SIDDQ |
>> +                     HOST_CTRL0_FORCESUSPEND |
>> +                     HOST_CTRL0_FORCESLEEP);
>> +
>> +     setbits_le32(&usb->usbphyctrl0,
>> +                     /* Setting up the ref freq */
>> +                     (CLK_24MHZ << 16) |
>> +                     /* HOST Phy setting */
>> +                     HOST_CTRL0_LINKSWRST |
>> +                     HOST_CTRL0_UTMISWRST);
>> +     udelay(10);
>> +     clrbits_le32(&usb->usbphyctrl0,
>> +                     HOST_CTRL0_LINKSWRST |
>> +                     HOST_CTRL0_UTMISWRST);
>> +     udelay(20);
>> +
>> +     /* EHCI Ctrl setting */
>> +     setbits_le32(&usb->ehcictrl,
>> +                     EHCICTRL_ENAINCRXALIGN |
>> +                     EHCICTRL_ENAINCR4 |
>> +                     EHCICTRL_ENAINCR8 |
>> +                     EHCICTRL_ENAINCR16);
>> +}
>> +
>> +/* Reset the EHCI host controller. */
>> +static void reset_usb_phy(struct exynos_usb_phy *usb)
>> +{
>> +     /* HOST_PHY reset */
>> +     setbits_le32(&usb->usbphyctrl0,
>> +                     HOST_CTRL0_PHYSWRST |
>> +                     HOST_CTRL0_PHYSWRSTALL |
>> +                     HOST_CTRL0_SIDDQ |
>> +                     HOST_CTRL0_FORCESUSPEND |
>> +                     HOST_CTRL0_FORCESLEEP);
>> +}
>> +
>> +/*
>> + * EHCI-initialization
>> + * Create the appropriate control structures to manage
>> + * a new EHCI host controller.
>> + */
>> +int ehci_hcd_init(void)
>> +{
>> +     struct exynos_usb_phy *usb;
>> +
>> +     usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
>> +     setup_usb_phy(usb);
>> +
>> +     hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci();
>> +     hcor = (struct ehci_hcor *)((uint32_t) hccr
>> +                             + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
>> +
>> +     debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
>> +             (uint32_t)hccr, (uint32_t)hcor,
>> +             (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
>> +
>> +     return 0;
>> +}
>> +
>> +/*
>> + * Destroy the appropriate control structures corresponding
>> + * the EHCI host controller.
>> + */
>> +int ehci_hcd_stop()
>> +{
>> +     struct exynos_usb_phy *usb;
>> +
>> +     usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
>> +     reset_usb_phy(usb);
>> +
>> +     return 0;
>> +}
>> diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
>> deleted file mode 100644
>> index 4dd4ec1..0000000
>> --- a/drivers/usb/host/ehci-s5p.c
>> +++ /dev/null
>> @@ -1,110 +0,0 @@
>> -/*
>> - * SAMSUNG S5P USB HOST EHCI Controller
>> - *
>> - * Copyright (C) 2012 Samsung Electronics Co.Ltd
>> - *   Vivek Gautam <gautam.vivek@samsung.com>
>> - *
>> - * This program is free software; you can redistribute it and/or
>> - * modify it under the terms of the GNU General Public License as
>> - * published by the Free Software Foundation; either version 2 of
>> - * the License, or (at your option) any later version.
>> - *
>> - * This program is distributed in the hope that it will be useful,
>> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> - * GNU General Public License for more details.
>> - *
>> - * You should have received a copy of the GNU General Public License
>> - * along with this program; if not, write to the Free Software
>> - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
>> - * MA 02110-1301 USA
>> - */
>> -
>> -#include <common.h>
>> -#include <usb.h>
>> -#include <asm/arch/cpu.h>
>> -#include <asm/arch/ehci-s5p.h>
>> -#include "ehci.h"
>> -#include "ehci-core.h"
>> -
>> -/* Setup the EHCI host controller. */
>> -static void setup_usb_phy(struct s5p_usb_phy *usb)
>> -{
>> -     clrbits_le32(&usb->usbphyctrl0,
>> -                     HOST_CTRL0_FSEL_MASK |
>> -                     HOST_CTRL0_COMMONON_N |
>> -                     /* HOST Phy setting */
>> -                     HOST_CTRL0_PHYSWRST |
>> -                     HOST_CTRL0_PHYSWRSTALL |
>> -                     HOST_CTRL0_SIDDQ |
>> -                     HOST_CTRL0_FORCESUSPEND |
>> -                     HOST_CTRL0_FORCESLEEP);
>> -
>> -     setbits_le32(&usb->usbphyctrl0,
>> -                     /* Setting up the ref freq */
>> -                     (CLK_24MHZ << 16) |
>> -                     /* HOST Phy setting */
>> -                     HOST_CTRL0_LINKSWRST |
>> -                     HOST_CTRL0_UTMISWRST);
>> -     udelay(10);
>> -     clrbits_le32(&usb->usbphyctrl0,
>> -                     HOST_CTRL0_LINKSWRST |
>> -                     HOST_CTRL0_UTMISWRST);
>> -     udelay(20);
>> -
>> -     /* EHCI Ctrl setting */
>> -     setbits_le32(&usb->ehcictrl,
>> -                     EHCICTRL_ENAINCRXALIGN |
>> -                     EHCICTRL_ENAINCR4 |
>> -                     EHCICTRL_ENAINCR8 |
>> -                     EHCICTRL_ENAINCR16);
>> -}
>> -
>> -/* Reset the EHCI host controller. */
>> -static void reset_usb_phy(struct s5p_usb_phy *usb)
>> -{
>> -     /* HOST_PHY reset */
>> -     setbits_le32(&usb->usbphyctrl0,
>> -                     HOST_CTRL0_PHYSWRST |
>> -                     HOST_CTRL0_PHYSWRSTALL |
>> -                     HOST_CTRL0_SIDDQ |
>> -                     HOST_CTRL0_FORCESUSPEND |
>> -                     HOST_CTRL0_FORCESLEEP);
>> -}
>> -
>> -/*
>> - * EHCI-initialization
>> - * Create the appropriate control structures to manage
>> - * a new EHCI host controller.
>> - */
>> -int ehci_hcd_init(void)
>> -{
>> -     struct s5p_usb_phy *usb;
>> -
>> -     usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();
>> -     setup_usb_phy(usb);
>> -
>> -     hccr = (struct ehci_hccr *)(EXYNOS5_USB_HOST_EHCI_BASE);
>> -     hcor = (struct ehci_hcor *)((uint32_t) hccr
>> -                             + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
>> -
>> -     debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
>> -             (uint32_t)hccr, (uint32_t)hcor,
>> -             (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
>> -
>> -     return 0;
>> -}
>> -
>> -/*
>> - * Destroy the appropriate control structures corresponding
>> - * the EHCI host controller.
>> - */
>> -int ehci_hcd_stop()
>> -{
>> -     struct s5p_usb_phy *usb;
>> -
>> -     usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();
>> -     reset_usb_phy(usb);
>> -
>> -     return 0;
>> -}
> _______________________________________________
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

Regards,
Rajeshwari Shinde.
Marek Vasut May 22, 2012, 5:16 a.m. UTC | #3 
Dear Rajeshwari Birje,

> Hi Marek,
> 
> On Tue, May 22, 2012 at 6:49 AM, Marek Vasut <marex@denx.de> wrote:
> > Dear Rajeshwari Shinde,
> > 
> >> This patch incorates the review comments given by Minkyu Kang for
> >> EHCI support on EXYNOS
> >> 
> >> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> > 
> > Perfect, applied and applied those 6 patches that were dangling. Now, I
> > pushed out new usb/master branch, can you please verify if it's all you
> > need from me before I submit another pull RQ?
> 
> Verified  all patches there.
> 
> > Sorry I wasn't really a textbook example of a maintainer, I hope we I'll
> > still see more code from you eventually.
> > 
> > Thank you very much for the work you put into these patches and all the
> > additional (unnecessary) hassle!
> 
> No problem. Thank you for incorporating them.

You're welcome.

[...]
> 
> Regards,
> Rajeshwari Shinde.

Best regards,
Marek Vasut
diff mbox

Patch

diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index ac4ddc7..85d421d 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -45,6 +45,7 @@ 
 #define EXYNOS4_USBOTG_BASE		0x12480000
 #define EXYNOS4_MMC_BASE		0x12510000
 #define EXYNOS4_SROMC_BASE		0x12570000
+#define EXYNOS4_USB_HOST_EHCI_BASE	0x12580000
 #define EXYNOS4_USBPHY_BASE		0x125B0000
 #define EXYNOS4_UART_BASE		0x13800000
 #define EXYNOS4_ADC_BASE		0x13910000
@@ -68,6 +69,7 @@ 
 #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE		0x11400000
 #define EXYNOS5_MIPI_DSIM_BASE		0x11D00000
+#define EXYNOS5_USB_HOST_EHCI_BASE	0x12110000
 #define EXYNOS5_MMC_BASE		0x12200000
 #define EXYNOS5_SROMC_BASE		0x12250000
 #define EXYNOS5_USBOTG_BASE		0x12480000
@@ -145,6 +147,7 @@  SAMSUNG_BASE(swreset, SWRESET)
 SAMSUNG_BASE(timer, PWMTIMER_BASE)
 SAMSUNG_BASE(uart, UART_BASE)
 SAMSUNG_BASE(usb_phy, USBPHY_BASE)
+SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
 SAMSUNG_BASE(usb_otg, USBOTG_BASE)
 SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 SAMSUNG_BASE(power, POWER_BASE)
diff --git a/arch/arm/include/asm/arch-exynos/ehci-s5p.h b/arch/arm/include/asm/arch-exynos/ehci-s5p.h
deleted file mode 100644
index 68feb85..0000000
--- a/arch/arm/include/asm/arch-exynos/ehci-s5p.h
+++ /dev/null
@@ -1,66 +0,0 @@ 
-/*
- * SAMSUNG S5P USB HOST EHCI Controller
- *
- * Copyright (C) 2012 Samsung Electronics Co.Ltd
- *	Vivek Gautam <gautam.vivek@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
-#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
-
-#define CLK_24MHZ		5
-
-#define HOST_CTRL0_PHYSWRSTALL			(1 << 31)
-#define HOST_CTRL0_COMMONON_N			(1 << 9)
-#define HOST_CTRL0_SIDDQ			(1 << 6)
-#define HOST_CTRL0_FORCESLEEP			(1 << 5)
-#define HOST_CTRL0_FORCESUSPEND			(1 << 4)
-#define HOST_CTRL0_WORDINTERFACE		(1 << 3)
-#define HOST_CTRL0_UTMISWRST			(1 << 2)
-#define HOST_CTRL0_LINKSWRST			(1 << 1)
-#define HOST_CTRL0_PHYSWRST			(1 << 0)
-
-#define HOST_CTRL0_FSEL_MASK			(7 << 16)
-
-#define EHCICTRL_ENAINCRXALIGN			(1 << 29)
-#define EHCICTRL_ENAINCR4			(1 << 28)
-#define EHCICTRL_ENAINCR8			(1 << 27)
-#define EHCICTRL_ENAINCR16			(1 << 26)
-
-/* Register map for PHY control */
-struct s5p_usb_phy {
-	unsigned int usbphyctrl0;
-	unsigned int usbphytune0;
-	unsigned int reserved1[2];
-	unsigned int hsicphyctrl1;
-	unsigned int hsicphytune1;
-	unsigned int reserved2[2];
-	unsigned int hsicphyctrl2;
-	unsigned int hsicphytune2;
-	unsigned int reserved3[2];
-	unsigned int ehcictrl;
-	unsigned int ohcictrl;
-	unsigned int usbotgsys;
-	unsigned int reserved4;
-	unsigned int usbotgtune;
-};
-
-/* Switch on the VBUS power. */
-int board_usb_vbus_init(void);
-
-#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */
diff --git a/arch/arm/include/asm/arch-exynos/ehci.h b/arch/arm/include/asm/arch-exynos/ehci.h
new file mode 100644
index 0000000..8aeff8a
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/ehci.h
@@ -0,0 +1,66 @@ 
+/*
+ * SAMSUNG EXYNOS USB HOST EHCI Controller
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ *	Vivek Gautam <gautam.vivek@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_EHCI_H__
+#define __ASM_ARM_ARCH_EHCI_H__
+
+#define CLK_24MHZ		5
+
+#define HOST_CTRL0_PHYSWRSTALL			(1 << 31)
+#define HOST_CTRL0_COMMONON_N			(1 << 9)
+#define HOST_CTRL0_SIDDQ			(1 << 6)
+#define HOST_CTRL0_FORCESLEEP			(1 << 5)
+#define HOST_CTRL0_FORCESUSPEND			(1 << 4)
+#define HOST_CTRL0_WORDINTERFACE		(1 << 3)
+#define HOST_CTRL0_UTMISWRST			(1 << 2)
+#define HOST_CTRL0_LINKSWRST			(1 << 1)
+#define HOST_CTRL0_PHYSWRST			(1 << 0)
+
+#define HOST_CTRL0_FSEL_MASK			(7 << 16)
+
+#define EHCICTRL_ENAINCRXALIGN			(1 << 29)
+#define EHCICTRL_ENAINCR4			(1 << 28)
+#define EHCICTRL_ENAINCR8			(1 << 27)
+#define EHCICTRL_ENAINCR16			(1 << 26)
+
+/* Register map for PHY control */
+struct exynos_usb_phy {
+	unsigned int usbphyctrl0;
+	unsigned int usbphytune0;
+	unsigned int reserved1[2];
+	unsigned int hsicphyctrl1;
+	unsigned int hsicphytune1;
+	unsigned int reserved2[2];
+	unsigned int hsicphyctrl2;
+	unsigned int hsicphytune2;
+	unsigned int reserved3[2];
+	unsigned int ehcictrl;
+	unsigned int ohcictrl;
+	unsigned int usbotgsys;
+	unsigned int reserved4;
+	unsigned int usbotgtune;
+};
+
+/* Switch on the VBUS power. */
+int board_usb_vbus_init(void);
+
+#endif /* __ASM_ARM_ARCH_EHCI_H__ */
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 59c3e57..645bb58 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -41,6 +41,7 @@  COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
 else
 COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
 endif
+COBJS-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
 COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
 COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
 COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
@@ -50,7 +51,6 @@  COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
 COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
 COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
 COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
-COBJS-$(CONFIG_USB_EHCI_S5P) += ehci-s5p.o
 COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 
diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c
new file mode 100644
index 0000000..3830c43
--- /dev/null
+++ b/drivers/usb/host/ehci-exynos.c
@@ -0,0 +1,110 @@ 
+/*
+ * SAMSUNG EXYNOS USB HOST EHCI Controller
+ *
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ *	Vivek Gautam <gautam.vivek@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ehci.h>
+#include "ehci.h"
+#include "ehci-core.h"
+
+/* Setup the EHCI host controller. */
+static void setup_usb_phy(struct exynos_usb_phy *usb)
+{
+	clrbits_le32(&usb->usbphyctrl0,
+			HOST_CTRL0_FSEL_MASK |
+			HOST_CTRL0_COMMONON_N |
+			/* HOST Phy setting */
+			HOST_CTRL0_PHYSWRST |
+			HOST_CTRL0_PHYSWRSTALL |
+			HOST_CTRL0_SIDDQ |
+			HOST_CTRL0_FORCESUSPEND |
+			HOST_CTRL0_FORCESLEEP);
+
+	setbits_le32(&usb->usbphyctrl0,
+			/* Setting up the ref freq */
+			(CLK_24MHZ << 16) |
+			/* HOST Phy setting */
+			HOST_CTRL0_LINKSWRST |
+			HOST_CTRL0_UTMISWRST);
+	udelay(10);
+	clrbits_le32(&usb->usbphyctrl0,
+			HOST_CTRL0_LINKSWRST |
+			HOST_CTRL0_UTMISWRST);
+	udelay(20);
+
+	/* EHCI Ctrl setting */
+	setbits_le32(&usb->ehcictrl,
+			EHCICTRL_ENAINCRXALIGN |
+			EHCICTRL_ENAINCR4 |
+			EHCICTRL_ENAINCR8 |
+			EHCICTRL_ENAINCR16);
+}
+
+/* Reset the EHCI host controller. */
+static void reset_usb_phy(struct exynos_usb_phy *usb)
+{
+	/* HOST_PHY reset */
+	setbits_le32(&usb->usbphyctrl0,
+			HOST_CTRL0_PHYSWRST |
+			HOST_CTRL0_PHYSWRSTALL |
+			HOST_CTRL0_SIDDQ |
+			HOST_CTRL0_FORCESUSPEND |
+			HOST_CTRL0_FORCESLEEP);
+}
+
+/*
+ * EHCI-initialization
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(void)
+{
+	struct exynos_usb_phy *usb;
+
+	usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
+	setup_usb_phy(usb);
+
+	hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci();
+	hcor = (struct ehci_hcor *)((uint32_t) hccr
+				+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+	debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
+		(uint32_t)hccr, (uint32_t)hcor,
+		(uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+	return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the EHCI host controller.
+ */
+int ehci_hcd_stop()
+{
+	struct exynos_usb_phy *usb;
+
+	usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
+	reset_usb_phy(usb);
+
+	return 0;
+}
diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
deleted file mode 100644
index 4dd4ec1..0000000
--- a/drivers/usb/host/ehci-s5p.c
+++ /dev/null
@@ -1,110 +0,0 @@ 
-/*
- * SAMSUNG S5P USB HOST EHCI Controller
- *
- * Copyright (C) 2012 Samsung Electronics Co.Ltd
- *	Vivek Gautam <gautam.vivek@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <usb.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/ehci-s5p.h>
-#include "ehci.h"
-#include "ehci-core.h"
-
-/* Setup the EHCI host controller. */
-static void setup_usb_phy(struct s5p_usb_phy *usb)
-{
-	clrbits_le32(&usb->usbphyctrl0,
-			HOST_CTRL0_FSEL_MASK |
-			HOST_CTRL0_COMMONON_N |
-			/* HOST Phy setting */
-			HOST_CTRL0_PHYSWRST |
-			HOST_CTRL0_PHYSWRSTALL |
-			HOST_CTRL0_SIDDQ |
-			HOST_CTRL0_FORCESUSPEND |
-			HOST_CTRL0_FORCESLEEP);
-
-	setbits_le32(&usb->usbphyctrl0,
-			/* Setting up the ref freq */
-			(CLK_24MHZ << 16) |
-			/* HOST Phy setting */
-			HOST_CTRL0_LINKSWRST |
-			HOST_CTRL0_UTMISWRST);
-	udelay(10);
-	clrbits_le32(&usb->usbphyctrl0,
-			HOST_CTRL0_LINKSWRST |
-			HOST_CTRL0_UTMISWRST);
-	udelay(20);
-
-	/* EHCI Ctrl setting */
-	setbits_le32(&usb->ehcictrl,
-			EHCICTRL_ENAINCRXALIGN |
-			EHCICTRL_ENAINCR4 |
-			EHCICTRL_ENAINCR8 |
-			EHCICTRL_ENAINCR16);
-}
-
-/* Reset the EHCI host controller. */
-static void reset_usb_phy(struct s5p_usb_phy *usb)
-{
-	/* HOST_PHY reset */
-	setbits_le32(&usb->usbphyctrl0,
-			HOST_CTRL0_PHYSWRST |
-			HOST_CTRL0_PHYSWRSTALL |
-			HOST_CTRL0_SIDDQ |
-			HOST_CTRL0_FORCESUSPEND |
-			HOST_CTRL0_FORCESLEEP);
-}
-
-/*
- * EHCI-initialization
- * Create the appropriate control structures to manage
- * a new EHCI host controller.
- */
-int ehci_hcd_init(void)
-{
-	struct s5p_usb_phy *usb;
-
-	usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();
-	setup_usb_phy(usb);
-
-	hccr = (struct ehci_hccr *)(EXYNOS5_USB_HOST_EHCI_BASE);
-	hcor = (struct ehci_hcor *)((uint32_t) hccr
-				+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
-
-	debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
-		(uint32_t)hccr, (uint32_t)hcor,
-		(uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
-
-	return 0;
-}
-
-/*
- * Destroy the appropriate control structures corresponding
- * the EHCI host controller.
- */
-int ehci_hcd_stop()
-{
-	struct s5p_usb_phy *usb;
-
-	usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();
-	reset_usb_phy(usb);
-
-	return 0;
-}