From patchwork Mon Dec 19 10:00:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 88447 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp1073272qgi; Mon, 19 Dec 2016 02:01:10 -0800 (PST) X-Received: by 10.98.204.138 with SMTP id j10mr14062842pfk.83.1482141670645; Mon, 19 Dec 2016 02:01:10 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h89si17830711pld.137.2016.12.19.02.01.10; Mon, 19 Dec 2016 02:01:10 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932610AbcLSKBJ (ORCPT + 4 others); Mon, 19 Dec 2016 05:01:09 -0500 Received: from mailout2.samsung.com ([203.254.224.25]:33288 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932235AbcLSKBJ (ORCPT ); Mon, 19 Dec 2016 05:01:09 -0500 Received: from epcpsbgm1new.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0OIF01NGLFTJ1K30@mailout2.samsung.com> for linux-samsung-soc@vger.kernel.org; Mon, 19 Dec 2016 19:01:07 +0900 (KST) X-AuditID: cbfee61a-f79bd6d000000fc6-71-5857afe3ca6b Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id 92.6D.04038.3EFA7585; Mon, 19 Dec 2016 19:01:07 +0900 (KST) Received: from AMDC2765.digital.local ([106.116.147.25]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OIF0060CFTEL470@mmp2.samsung.com>; Mon, 19 Dec 2016 19:01:07 +0900 (KST) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH v3] arm: dts: exynos: Enable DMA support for UART modules on Exynos5 SoCs Date: Mon, 19 Dec 2016 11:00:48 +0100 Message-id: <1482141648-21294-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1481891940-10385-1-git-send-email-m.szyprowski@samsung.com> References: <1481891940-10385-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrFLMWRmVeSWpSXmKPExsVy+t9jQd3H68MjDO5e5bHYOGM9q8X58xvY LWac38dksfbIXXaLw2/aWR1YPTat6mTz6NuyitHj8ya5AOYoN5uM1MSU1CKF1Lzk/JTMvHRb pdAQN10LJYW8xNxUW6UIXd+QICWFssScUiDPyAANODgHuAcr6dsluGUs2HaOtWCvTMW2c38Y Gxgni3cxcnJICJhILL54lxnCFpO4cG89WxcjF4eQwCxGiZsTTjBCOL8YJab838QOUsUmYCjR 9baLDcQWEVCV+Ny2gB2kiFlgP6PE+a3PwEYJC0RLHD7fClbEAlR0e8MvFhCbV8BDYvLpp+wQ 6+QkTh6bzApicwp4SqzrfQYWFwKqeXD7INMERt4FjAyrGCVSC5ILipPScw3zUsv1ihNzi0vz 0vWS83M3MYLD9ZnUDsaDu9wPMQpwMCrx8Ba8D4sQYk0sK67MPcQowcGsJMLbviY8Qog3JbGy KrUoP76oNCe1+BCjKdBhE5mlRJPzgbGUVxJvaGJuYm5sYGFuaWlipCTO2zj7WbiQQHpiSWp2 ampBahFMHxMHp1QDo7mLgMStBead1atmeQcfqE6UKzE2dUr8s+nmi+1WXBpnV/jsq3UrFA81 iv7QvSu+3iLxUO3OVr1V9n4fFUW6GnW7t3+NnXJ6voD5Qo2tL95uufOOJd+n6knZauf/W17c CecrXXZxnsfRa/dvrzyx4KTK3iXRUes2rpbP07HM+qKevsLq0ZyCB0osxRmJhlrMRcWJAFZ/ st5tAgAA X-MTR: 20000000000000000@CPGS Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org UART modules can use DMA for offloading data transfers and reducing interrupts, so enable this feature for Exynos5 boards. Tested on Google ChromeBook Snow (Exynos5250), Odroid XU (Exynos5410) and Odroid XU3 (Exynos5422) boards. Signed-off-by: Marek Szyprowski --- v3: - added Exynos5410 - fixed serial 1/2 again, in v2 they were incorrectly swaped as a result of my hurry in patch posting v2: - added Exynos5250 - fixed copy/paste typo for serial 2 and 3 --- arch/arm/boot/dts/exynos5250.dtsi | 8 ++++++++ arch/arm/boot/dts/exynos5410.dtsi | 8 ++++++++ arch/arm/boot/dts/exynos5420.dtsi | 8 ++++++++ 3 files changed, 24 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Tested-by: Alim Akhtar diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index b6d7444..0e04460 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -1043,21 +1043,29 @@ &serial_0 { clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma0 13>, <&pdma0 14>; + dma-names = "rx", "tx"; }; &serial_1 { clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma1 15>, <&pdma1 16>; + dma-names = "rx", "tx"; }; &serial_2 { clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma0 15>, <&pdma0 16>; + dma-names = "rx", "tx"; }; &serial_3 { clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma1 17>, <&pdma1 18>; + dma-names = "rx", "tx"; }; #include "exynos5250-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 2b6adaf..7eab4bc 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -340,21 +340,29 @@ &serial_0 { clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma0 13>, <&pdma0 14>; + dma-names = "rx", "tx"; }; &serial_1 { clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma1 15>, <&pdma1 16>; + dma-names = "rx", "tx"; }; &serial_2 { clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma0 15>, <&pdma0 16>; + dma-names = "rx", "tx"; }; &serial_3 { clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma1 17>, <&pdma1 18>; + dma-names = "rx", "tx"; }; &sss { diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 906a1a4..0154c2e 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -1406,21 +1406,29 @@ &serial_0 { clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma0 13>, <&pdma0 14>; + dma-names = "rx", "tx"; }; &serial_1 { clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma1 15>, <&pdma1 16>; + dma-names = "rx", "tx"; }; &serial_2 { clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma0 15>, <&pdma0 16>; + dma-names = "rx", "tx"; }; &serial_3 { clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; clock-names = "uart", "clk_uart_baud0"; + dmas = <&pdma1 17>, <&pdma1 18>; + dma-names = "rx", "tx"; }; &sss {