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[209.132.180.131]) by mx.google.com with ESMTPS id u22si38741262plj.0.2017.01.01.09.16.32 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 01 Jan 2017 09:16:33 -0800 (PST) Received-SPF: pass (google.com: domain of gdb-patches-return-135944-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org; spf=pass (google.com: domain of gdb-patches-return-135944-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gdb-patches-return-135944-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :cc:content-type; q=dns; s=default; b=BCL5VYWR10Ej+9T1cp8R2CmIch aTg72Aj3EeGVxk49n4L+PvyXvWTLCx642qsCjIbpz0er8hXySbXGQAYgUw28CNWq CGFoh27GF21VLtFIgAM8XU4b3rDenQv9w6RHDt37WBLGquVYrJILYw8vx/+9az6W gt88EJ58DfETUpQtg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :cc:content-type; s=default; bh=8yqz/y5zjtBNApM3/py1e7JKCto=; b= M1T0gjQycE906SH3AEZYUlyM2t97cVlAfEm7zz40woB6jmjdiOx2XckjQjU/kFsK 4d23/xRaYOg9M+rDWSO6caZ4rHxvB8B2rUFZ7becwIV2Gb05reGMpPk1q6G3p+GP SuOsv1ciuuxPjPaaVLvZdYQDu9J2Zhm6scWi6kEaAgs= Received: (qmail 93681 invoked by alias); 1 Jan 2017 17:16:26 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 93668 invoked by uid 89); 1 Jan 2017 17:16:24 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.4 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=no version=3.3.2 spammy=fpclassify, isnan, 1, 82 X-HELO: mail-yw0-f169.google.com Received: from mail-yw0-f169.google.com (HELO mail-yw0-f169.google.com) (209.85.161.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 01 Jan 2017 17:16:14 +0000 Received: by mail-yw0-f169.google.com with SMTP id t125so255626896ywc.1 for ; Sun, 01 Jan 2017 09:16:14 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=Hk6bFCivrTN8u94BZv586HevEfr24MgFl8a+4ZESCts=; b=d7SK+xXGye/q+sXi43B73mJHN6b9AkMr7lQwjInTyL2CDOVkLFm8iZr2L5A/yLuEtn hb13FTLzTQXpM8KTYaHjxUrJM5FTbjqDyyS4P/wulIBxTyvo2QgFcgjjwwPr0+uT79FS GBnFmQrhmV+9/weyNZLPkZcJ6zhe1smtkXPrK+pxewBGEj5dbFbaMBNyzpi3khjnTzrY 6xrFnO1hEaL6LSonAJCLEj/NCcHvwIYr+bgDWLp0w+81C+7cryH4ZAEpxa4/qX21hLEh 88js4Oi8MWMDqSq0OT2DS4EFcyaCTnrX87LIOIIxfzdxeNDjGHXssykfezJWdlJTwAod mNQg== X-Gm-Message-State: AIkVDXJgqsXQmYdhoD36e3GmoHfSFdfdDkUwyLA25UMuanViLaajpQqB5L5R9/GP6FAPSNoLn1SUwY8yFejqBbU4 X-Received: by 10.129.109.200 with SMTP id i191mr50733588ywc.14.1483290973248; Sun, 01 Jan 2017 09:16:13 -0800 (PST) MIME-Version: 1.0 Received: by 10.129.92.4 with HTTP; Sun, 1 Jan 2017 09:16:12 -0800 (PST) From: Jim Wilson Date: Sun, 1 Jan 2017 09:16:12 -0800 Message-ID: Subject: [PATCH] aarch64 sim fp min/max number bug fix To: gdb-patches@sourceware.org Cc: Nick Clifton The fp min/max number routines are using fpclassify to try to distinguish between a nan and a number, but this is handling zero, inf, and subnormals incorrectly. We get the right result if we just use isnan. The testcase works with the patch, and fails without the patch. The patch also reduces GCC C testsuite failures from 2416 to 2407. Jim sim/aarch64/ * simulator.c (fmaxnm): Use isnan instead of fpclassify. (fminnm, dmaxnm, dminnm): Likewise. sim/testsuite/sim/aarch64/ * fminnm.s: New. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index be3d6c7..cf65a51 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -3831,13 +3831,13 @@ do_vec_MLA (sim_cpu *cpu) static float fmaxnm (float a, float b) { - if (fpclassify (a) == FP_NORMAL) + if (! isnan (a)) { - if (fpclassify (b) == FP_NORMAL) + if (! isnan (b)) return a > b ? a : b; return a; } - else if (fpclassify (b) == FP_NORMAL) + else if (! isnan (b)) return b; return a; } @@ -3845,13 +3845,13 @@ fmaxnm (float a, float b) static float fminnm (float a, float b) { - if (fpclassify (a) == FP_NORMAL) + if (! isnan (a)) { - if (fpclassify (b) == FP_NORMAL) + if (! isnan (b)) return a < b ? a : b; return a; } - else if (fpclassify (b) == FP_NORMAL) + else if (! isnan (b)) return b; return a; } @@ -3859,13 +3859,13 @@ fminnm (float a, float b) static double dmaxnm (double a, double b) { - if (fpclassify (a) == FP_NORMAL) + if (! isnan (a)) { - if (fpclassify (b) == FP_NORMAL) + if (! isnan (b)) return a > b ? a : b; return a; } - else if (fpclassify (b) == FP_NORMAL) + else if (! isnan (b)) return b; return a; } @@ -3873,13 +3873,13 @@ dmaxnm (double a, double b) static double dminnm (double a, double b) { - if (fpclassify (a) == FP_NORMAL) + if (! isnan (a)) { - if (fpclassify (b) == FP_NORMAL) + if (! isnan (b)) return a < b ? a : b; return a; } - else if (fpclassify (b) == FP_NORMAL) + else if (! isnan (b)) return b; return a; } diff --git a/sim/testsuite/sim/aarch64/fminnm.s b/sim/testsuite/sim/aarch64/fminnm.s new file mode 100644 index 0000000..43ccd7c --- /dev/null +++ b/sim/testsuite/sim/aarch64/fminnm.s @@ -0,0 +1,82 @@ +# mach: aarch64 + +# Check the FP min/max number instructions: fminnm, fmaxnm, dminnm, dmaxnm. +# For min, check 2/1, 1/0, -1/-Inf. +# For max, check 1/2, -1/0, 1/+inf. + +.include "testutils.inc" + + start + fmov s0, #2.0 + fmov s1, #1.0 + fminnm s2, s0, s1 + fcmp s2, s1 + bne .Lfailure + fmov d0, #2.0 + fmov d1, #1.0 + fminnm d2, d0, d1 + fcmp d2, d1 + bne .Lfailure + + fmov s0, #1.0 + fmov s1, wzr + fminnm s2, s0, s1 + fcmp s2, s1 + bne .Lfailure + fmov d0, #1.0 + fmov d1, xzr + fminnm d2, d0, d1 + fcmp d2, d1 + bne .Lfailure + + fmov s0, #-1.0 + fmov s1, wzr + fdiv s1, s0, s1 + fminnm s2, s0, s1 + fcmp s2, s1 + bne .Lfailure + fmov d0, #-1.0 + fmov d1, xzr + fdiv d1, d0, d1 + fminnm d1, d0, d1 + fcmp d0, d0 + bne .Lfailure + + fmov s0, #1.0 + fmov s1, #2.0 + fmaxnm s2, s0, s1 + fcmp s2, s1 + bne .Lfailure + fmov d0, #1.0 + fmov d1, #2.0 + fmaxnm d2, d0, d1 + fcmp d2, d1 + bne .Lfailure + + fmov s0, #-1.0 + fmov s1, wzr + fmaxnm s2, s0, s1 + fcmp s2, s1 + bne .Lfailure + fmov d0, #-1.0 + fmov d1, xzr + fmaxnm d2, d0, d1 + fcmp d2, d1 + bne .Lfailure + + fmov s0, #1.0 + fmov s1, wzr + fdiv s1, s0, s1 + fmaxnm s2, s0, s1 + fcmp s2, s1 + bne .Lfailure + fmov d0, #1.0 + fmov d1, xzr + fdiv d1, d0, d1 + fmaxnm d1, d0, d1 + fcmp d0, d0 + bne .Lfailure + + pass +.Lfailure: + fail