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[209.132.180.131]) by mx.google.com with ESMTPS id d74si82414pfd.278.2017.01.06.07.12.37 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 06 Jan 2017 07:12:37 -0800 (PST) Received-SPF: pass (google.com: domain of gdb-patches-return-136039-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org; spf=pass (google.com: domain of gdb-patches-return-136039-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gdb-patches-return-136039-patch=linaro.org@sourceware.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:subject:to:references:cc:from:message-id:date :mime-version:in-reply-to:content-type; q=dns; s=default; b=oiOW wVKVlu/QyTijCGCBvTi1Si/yBoZCPXdMATsfe01+GxWHsCfzms78MFPmdYFfQ2qq ju+aeVUCsmMHAqK1e9wAh2t+q/wbgjwzENOXvxOiI06BWEh5Iprt/Mu4hUwv+x1W gWO5q4LeI3Ob56mvZljt3cmM0RKtpQUNw5eDiok= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:subject:to:references:cc:from:message-id:date :mime-version:in-reply-to:content-type; s=default; bh=+L1Ou5UwbQ Prrzm1dkpRrqDObCo=; b=oa3svly3/nh0qtR6SkebRh5ZC9gr8J5ojqlJiRGmwh Yo97faWZkBAjj7rYnp80z+YdNZg7JAwVK04+AugP8as8JzheYo7pwW6pIzBZ9PiO O+pyCrYSjrgtZG2Mjs+JjcKQwU++mdsVakz9YLnTVh/IBBNJoaeZaEYQLFiDUwtI c= Received: (qmail 38889 invoked by alias); 6 Jan 2017 15:12:29 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 38843 invoked by uid 89); 6 Jan 2017 15:12:26 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-5.1 required=5.0 tests=BAYES_00, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=512017, H*f:sk:082f9ac, Raw, f46 X-HELO: userp1040.oracle.com Received: from userp1040.oracle.com (HELO userp1040.oracle.com) (156.151.31.81) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 06 Jan 2017 15:12:16 +0000 Received: from userv0022.oracle.com (userv0022.oracle.com [156.151.31.74]) by userp1040.oracle.com (Sentrion-MTA-4.3.2/Sentrion-MTA-4.3.2) with ESMTP id v06FCCnA011003 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 6 Jan 2017 15:12:13 GMT Received: from userv0121.oracle.com (userv0121.oracle.com [156.151.31.72]) by userv0022.oracle.com (8.14.4/8.14.4) with ESMTP id v06FCCud020173 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 6 Jan 2017 15:12:12 GMT Received: from abhmp0001.oracle.com (abhmp0001.oracle.com [141.146.116.7]) by userv0121.oracle.com (8.14.4/8.13.8) with ESMTP id v06FCBfV009097; Fri, 6 Jan 2017 15:12:12 GMT Received: from [10.175.233.210] (/10.175.233.210) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Fri, 06 Jan 2017 07:12:11 -0800 Subject: Re: [PATCH] Bug 20936 - provide sparc and sparcv9 target description XML files To: Yao Qi References: <46200a1e-29f7-8e20-c0b5-3f6f25c82d45@oracle.com> <20161206152616.GC28789@E107787-LIN> <83d4c58d-0834-4fc2-6194-72408510aa8a@oracle.com> <20161212125331.GB25542@E107787-LIN> <082f9ac8-3e46-42cd-198d-91866d83ebb8@oracle.com> <20170105143109.GA21293@E107787-LIN> Cc: gdb-patches@sourceware.org From: Ivo Raisr Message-ID: Date: Fri, 6 Jan 2017 16:12:09 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <20170105143109.GA21293@E107787-LIN> On 5.1.2017 15:31, Yao Qi wrote: > On 17-01-04 18:42:27, Ivo Raisr wrote: >> On 12.12.2016 13:53, Yao Qi wrote: >> >>> Hi Ivo, >>> Your patch does two orthogonal things IMO, >>> >>> - Pseudo register support enhancement, patch #1 >>> - XML target description support and sparc*-tdep.c updates, patch #2, >>> >>> Can you split them to two patches? >> Hi Yao, >> >> Thank you for looking into my changes. >> I think I can see your motivation behind splitting the patch into two, >> for better readability and manageability. >> However my intention was only to provide support for registers >> supplied by target description (Valgrind shadow registers in addition >> to sparc real hardware ones). >> Pseudo register changes were just a necessity to get this done >> because Valgrind shadow registers are considered as "real" registers >> and thus they are numbered before any pseudo registers. >> This also means I cannot draw a clear line between your suggested >> patch #1 and #2. Can you take my whole patch as is? >> > The line is clear to me. I split your patch, and show the patch #1 here. > Does it work for you? Note you still need to add comments to new functions > in the patch below. I think I see the line now as well. Please find patch #1 together with a ChangeLog entry. The patch was successfully built and tested on Solaris sparc. After you find it ok, I will prepare patch #2. I. ChangeLog entry: 2017-01-06 Ivo Raisr Split real and pseudo registers in preparation for registers provided by a target. Registers provided by target description can have more real registers and pseudo registers need to be positioned after them. * sparc-tdep.h: Separate real and pseudo registers. * sparc64-tdep.h: Separate real and pseudo registers. * sparc-tdep.c (sparc32_pseudo_register_name): New function returning pseudo register names on sparc 32-bit. (sparc32_register_name): Use sparc32_pseudo_register_name(). (sparc32_pseudo_register_type): New function returning pseudo register types on sparc 32-bit. (sparc32_register_type): Use sparc32_pseudo_register_type(). (sparc32_pseudo_register_read, sparc32_pseudo_register_write): Pseudo registers may have different numbers. (sparc32_gdbarch_init): Initialize properly sparc 32-bit register names. * sparc64-tdep.c (sparc64_pseudo_register_name): New function returning pseudo register names on sparc 64-bit. (sparc64_register_name): Use sparc64_pseudo_register_name(). (sparc64_pseudo_register_type): New function returning pseudo register types on sparc 64-bit. (sparc64_register_type): Use sparc64_pseudo_register_type(). (sparc64_pseudo_register_read, sparc64_pseudo_register_write): Pseudo registers may have different numbers. (sparc64_store_floating_fields, sparc64_extract_floating_fields, sparc64_store_arguments): Pseudo registers may have different numbers; deal with it. (sparc64_init_abi): Initialize properly sparc 64-bit register names. --- a/gdb/sparc-tdep.h 2016-02-09 19:19:39.000000000 +0000 +++ b/gdb/sparc-tdep.h 2017-01-06 04:12:14.291269940 +0000 @@ -20,6 +20,12 @@ #ifndef SPARC_TDEP_H #define SPARC_TDEP_H 1 +#define SPARC_CORE_REGISTERS \ + "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \ + "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", \ + "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", \ + "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7" + struct frame_info; struct gdbarch; struct regcache; @@ -57,6 +63,12 @@ struct gdbarch_tdep int pc_regnum; int npc_regnum; + /* Register names specific for architecture (sparc32 vs. sparc64) */ + const char **fpu_register_names; + size_t fpu_registers_num; + const char **cp0_register_names; + size_t cp0_registers_num; + /* Register sets. */ const struct regset *gregset; size_t sizeof_gregset; @@ -85,7 +97,7 @@ struct gdbarch_tdep enum sparc_regnum { - SPARC_G0_REGNUM, /* %g0 */ + SPARC_G0_REGNUM = 0, /* %g0 */ SPARC_G1_REGNUM, SPARC_G2_REGNUM, SPARC_G3_REGNUM, @@ -140,9 +152,12 @@ enum sparc32_regnum SPARC32_NPC_REGNUM, /* %npc */ SPARC32_FSR_REGNUM, /* %fsr */ SPARC32_CSR_REGNUM, /* %csr */ +}; - /* Pseudo registers. */ - SPARC32_D0_REGNUM, /* %d0 */ +/* Pseudo registers. */ +enum sparc32_pseudo_regnum +{ + SPARC32_D0_REGNUM = 0, /* %d0 */ SPARC32_D30_REGNUM /* %d30 */ = SPARC32_D0_REGNUM + 15 }; --- a/gdb/sparc-tdep.c 2016-02-09 19:19:39.000000000 +0000 +++ b/gdb/sparc-tdep.c 2017-01-06 04:12:14.293179005 +0000 @@ -295,20 +295,23 @@ sparc_structure_or_union_p (const struct } /* Register information. */ +#define SPARC32_FPU_REGISTERS \ + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" +#define SPARC32_CP0_REGISTERS \ + "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" + +static const char *sparc_core_register_names[] = { SPARC_CORE_REGISTERS }; +static const char *sparc32_fpu_register_names[] = { SPARC32_FPU_REGISTERS }; +static const char *sparc32_cp0_register_names[] = { SPARC32_CP0_REGISTERS }; static const char *sparc32_register_names[] = { - "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", - "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", - "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", - "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", - - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", - - "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" + SPARC_CORE_REGISTERS, + SPARC32_FPU_REGISTERS, + SPARC32_CP0_REGISTERS }; /* Total number of registers. */ @@ -327,17 +330,26 @@ static const char *sparc32_pseudo_regist #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) /* Return the name of register REGNUM. */ +static const char * +sparc32_pseudo_register_name (struct gdbarch *gdbarch, int regnum) +{ + regnum -= gdbarch_num_regs (gdbarch); + + if (regnum < SPARC32_NUM_PSEUDO_REGS) + return sparc32_pseudo_register_names[regnum]; + + internal_error (__FILE__, __LINE__, + _("sparc32_pseudo_register_name: bad register number %d"), + regnum); +} static const char * sparc32_register_name (struct gdbarch *gdbarch, int regnum) { - if (regnum >= 0 && regnum < SPARC32_NUM_REGS) + if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) return sparc32_register_names[regnum]; - if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) - return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; - - return NULL; + return sparc32_pseudo_register_name (gdbarch, regnum); } /* Construct types for ISA-specific registers. */ @@ -399,6 +411,18 @@ sparc_fsr_type (struct gdbarch *gdbarch) /* Return the GDB type object for the "standard" data type of data in register REGNUM. */ +static struct type * +sparc32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) +{ + regnum -= gdbarch_num_regs (gdbarch); + + if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) + return builtin_type (gdbarch)->builtin_double; + + internal_error (__FILE__, __LINE__, + _("sparc32_pseudo_register_type: bad register number %d"), + regnum); +} static struct type * sparc32_register_type (struct gdbarch *gdbarch, int regnum) @@ -406,9 +430,6 @@ sparc32_register_type (struct gdbarch *g if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) return builtin_type (gdbarch)->builtin_float; - if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) - return builtin_type (gdbarch)->builtin_double; - if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) return builtin_type (gdbarch)->builtin_data_ptr; @@ -421,6 +442,9 @@ sparc32_register_type (struct gdbarch *g if (regnum == SPARC32_FSR_REGNUM) return sparc_fsr_type (gdbarch); + if (regnum >= gdbarch_num_regs (gdbarch)) + return sparc32_pseudo_register_type (gdbarch, regnum); + return builtin_type (gdbarch)->builtin_int32; } @@ -431,6 +455,7 @@ sparc32_pseudo_register_read (struct gdb { enum register_status status; + regnum -= gdbarch_num_regs (gdbarch); gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); @@ -445,6 +470,7 @@ sparc32_pseudo_register_write (struct gd struct regcache *regcache, int regnum, const gdb_byte *buf) { + regnum -= gdbarch_num_regs (gdbarch); gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); @@ -1678,6 +1704,10 @@ sparc32_gdbarch_init (struct gdbarch_inf tdep->pc_regnum = SPARC32_PC_REGNUM; tdep->npc_regnum = SPARC32_NPC_REGNUM; tdep->step_trap = sparc_step_trap; + tdep->fpu_register_names = sparc32_fpu_register_names; + tdep->fpu_registers_num = ARRAY_SIZE (sparc32_fpu_register_names); + tdep->cp0_register_names = sparc32_cp0_register_names; + tdep->cp0_registers_num = ARRAY_SIZE (sparc32_cp0_register_names); set_gdbarch_long_double_bit (gdbarch, 128); set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); --- a/gdb/sparc64-tdep.h 2016-02-09 19:19:39.000000000 +0000 +++ b/gdb/sparc64-tdep.h 2017-01-06 04:12:14.294032452 +0000 @@ -56,9 +56,12 @@ enum sparc64_regnum SPARC64_FSR_REGNUM, /* %fsr */ SPARC64_FPRS_REGNUM, /* %fprs */ SPARC64_Y_REGNUM, /* %y */ +}; - /* Pseudo registers. */ - SPARC64_CWP_REGNUM, /* %cwp */ +/* Pseudo registers. */ +enum sparc64_pseudo_regnum +{ + SPARC64_CWP_REGNUM = 0, /* %cwp */ SPARC64_PSTATE_REGNUM, /* %pstate */ SPARC64_ASI_REGNUM, /* %asi */ SPARC64_CCR_REGNUM, /* %ccr */ --- a/gdb/sparc64-tdep.c 2016-02-09 19:19:39.000000000 +0000 +++ b/gdb/sparc64-tdep.c 2017-01-06 04:12:14.295659262 +0000 @@ -226,28 +226,29 @@ sparc64_fprs_type (struct gdbarch *gdbar /* Register information. */ +#define SPARC64_FPU_REGISTERS \ + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \ + "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46", \ + "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62" +#define SPARC64_CP0_REGISTERS \ + "pc", "npc", \ + /* FIXME: Give "state" a name until we start using register groups. */ \ + "state", \ + "fsr", \ + "fprs", \ + "y" + +static const char *sparc64_fpu_register_names[] = { SPARC64_FPU_REGISTERS }; +static const char *sparc64_cp0_register_names[] = { SPARC64_CP0_REGISTERS }; static const char *sparc64_register_names[] = { - "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", - "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", - "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", - "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", - - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", - "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46", - "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62", - - "pc", "npc", - - /* FIXME: Give "state" a name until we start using register groups. */ - "state", - "fsr", - "fprs", - "y", + SPARC_CORE_REGISTERS, + SPARC64_FPU_REGISTERS, + SPARC64_CP0_REGISTERS }; /* Total number of registers. */ @@ -273,28 +274,57 @@ static const char *sparc64_pseudo_regist #define SPARC64_NUM_PSEUDO_REGS ARRAY_SIZE (sparc64_pseudo_register_names) /* Return the name of register REGNUM. */ +static const char * +sparc64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) +{ + regnum -= gdbarch_num_regs (gdbarch); + + if (regnum < SPARC64_NUM_PSEUDO_REGS) + return sparc64_pseudo_register_names[regnum]; + + internal_error (__FILE__, __LINE__, + _("sparc64_pseudo_register_name: bad register number %d"), + regnum); +} static const char * sparc64_register_name (struct gdbarch *gdbarch, int regnum) { - if (regnum >= 0 && regnum < SPARC64_NUM_REGS) + if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) return sparc64_register_names[regnum]; - if (regnum >= SPARC64_NUM_REGS - && regnum < SPARC64_NUM_REGS + SPARC64_NUM_PSEUDO_REGS) - return sparc64_pseudo_register_names[regnum - SPARC64_NUM_REGS]; - - return NULL; + return sparc64_pseudo_register_name (gdbarch, regnum); } /* Return the GDB type object for the "standard" data type of data in register REGNUM. */ +static struct type * +sparc64_pseudo_register_type (struct gdbarch *gdbarch, int regnum) +{ + regnum -= gdbarch_num_regs (gdbarch); + + if (regnum == SPARC64_CWP_REGNUM) + return builtin_type (gdbarch)->builtin_int64; + if (regnum == SPARC64_PSTATE_REGNUM) + return sparc64_pstate_type (gdbarch); + if (regnum == SPARC64_ASI_REGNUM) + return builtin_type (gdbarch)->builtin_int64; + if (regnum == SPARC64_CCR_REGNUM) + return builtin_type (gdbarch)->builtin_int64; + if (regnum >= SPARC64_D0_REGNUM && regnum <= SPARC64_D62_REGNUM) + return builtin_type (gdbarch)->builtin_double; + if (regnum >= SPARC64_Q0_REGNUM && regnum <= SPARC64_Q60_REGNUM) + return builtin_type (gdbarch)->builtin_long_double; + + internal_error (__FILE__, __LINE__, + _("sparc64_pseudo_register_type: bad register number %d"), + regnum); +} static struct type * sparc64_register_type (struct gdbarch *gdbarch, int regnum) { /* Raw registers. */ - if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) return builtin_type (gdbarch)->builtin_data_ptr; if (regnum >= SPARC_G0_REGNUM && regnum <= SPARC_I7_REGNUM) @@ -319,19 +349,8 @@ sparc64_register_type (struct gdbarch *g return builtin_type (gdbarch)->builtin_int64; /* Pseudo registers. */ - - if (regnum == SPARC64_CWP_REGNUM) - return builtin_type (gdbarch)->builtin_int64; - if (regnum == SPARC64_PSTATE_REGNUM) - return sparc64_pstate_type (gdbarch); - if (regnum == SPARC64_ASI_REGNUM) - return builtin_type (gdbarch)->builtin_int64; - if (regnum == SPARC64_CCR_REGNUM) - return builtin_type (gdbarch)->builtin_int64; - if (regnum >= SPARC64_D0_REGNUM && regnum <= SPARC64_D62_REGNUM) - return builtin_type (gdbarch)->builtin_double; - if (regnum >= SPARC64_Q0_REGNUM && regnum <= SPARC64_Q60_REGNUM) - return builtin_type (gdbarch)->builtin_long_double; + if (regnum >= gdbarch_num_regs (gdbarch)) + return sparc64_pseudo_register_type (gdbarch, regnum); internal_error (__FILE__, __LINE__, _("invalid regnum")); } @@ -344,7 +363,7 @@ sparc64_pseudo_register_read (struct gdb enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); enum register_status status; - gdb_assert (regnum >= SPARC64_NUM_REGS); + regnum -= gdbarch_num_regs (gdbarch); if (regnum >= SPARC64_D0_REGNUM && regnum <= SPARC64_D30_REGNUM) { @@ -421,7 +440,8 @@ sparc64_pseudo_register_write (struct gd int regnum, const gdb_byte *buf) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); - gdb_assert (regnum >= SPARC64_NUM_REGS); + + regnum -= gdbarch_num_regs (gdbarch); if (regnum >= SPARC64_D0_REGNUM && regnum <= SPARC64_D30_REGNUM) { @@ -638,6 +658,7 @@ static void sparc64_store_floating_fields (struct regcache *regcache, struct type *type, const gdb_byte *valbuf, int element, int bitpos) { + struct gdbarch *gdbarch = get_regcache_arch (regcache); int len = TYPE_LENGTH (type); gdb_assert (element < 16); @@ -652,14 +673,15 @@ sparc64_store_floating_fields (struct re gdb_assert (bitpos == 0); gdb_assert ((element % 2) == 0); - regnum = SPARC64_Q0_REGNUM + element / 2; + regnum = gdbarch_num_regs (gdbarch) + SPARC64_Q0_REGNUM + element / 2; regcache_cooked_write (regcache, regnum, valbuf); } else if (len == 8) { gdb_assert (bitpos == 0 || bitpos == 64); - regnum = SPARC64_D0_REGNUM + element + bitpos / 64; + regnum = gdbarch_num_regs (gdbarch) + SPARC64_D0_REGNUM + + element + bitpos / 64; regcache_cooked_write (regcache, regnum, valbuf + (bitpos / 8)); } else @@ -712,6 +734,8 @@ static void sparc64_extract_floating_fields (struct regcache *regcache, struct type *type, gdb_byte *valbuf, int bitpos) { + struct gdbarch *gdbarch = get_regcache_arch (regcache); + if (sparc64_floating_p (type)) { int len = TYPE_LENGTH (type); @@ -721,14 +745,15 @@ sparc64_extract_floating_fields (struct { gdb_assert (bitpos == 0 || bitpos == 128); - regnum = SPARC64_Q0_REGNUM + bitpos / 128; + regnum = gdbarch_num_regs (gdbarch) + SPARC64_Q0_REGNUM + + bitpos / 128; regcache_cooked_read (regcache, regnum, valbuf + (bitpos / 8)); } else if (len == 8) { gdb_assert (bitpos % 64 == 0 && bitpos >= 0 && bitpos < 256); - regnum = SPARC64_D0_REGNUM + bitpos / 64; + regnum = gdbarch_num_regs (gdbarch) + SPARC64_D0_REGNUM + bitpos / 64; regcache_cooked_read (regcache, regnum, valbuf + (bitpos / 8)); } else @@ -911,13 +936,13 @@ sparc64_store_arguments (struct regcache /* Float Complex or double Complex arguments. */ if (element < 16) { - regnum = SPARC64_D0_REGNUM + element; + regnum = gdbarch_num_regs (gdbarch) + SPARC64_D0_REGNUM + element; if (len == 16) { - if (regnum < SPARC64_D30_REGNUM) + if (regnum < gdbarch_num_regs (gdbarch) + SPARC64_D30_REGNUM) regcache_cooked_write (regcache, regnum + 1, valbuf + 8); - if (regnum < SPARC64_D10_REGNUM) + if (regnum < gdbarch_num_regs (gdbarch) + SPARC64_D10_REGNUM) regcache_cooked_write (regcache, SPARC_O0_REGNUM + element + 1, valbuf + 8); @@ -932,12 +957,14 @@ sparc64_store_arguments (struct regcache if (element % 2) element++; if (element < 16) - regnum = SPARC64_Q0_REGNUM + element / 2; + regnum = gdbarch_num_regs (gdbarch) + SPARC64_Q0_REGNUM + + element / 2; } else if (len == 8) { if (element < 16) - regnum = SPARC64_D0_REGNUM + element; + regnum = gdbarch_num_regs (gdbarch) + SPARC64_D0_REGNUM + + element; } else if (len == 4) { @@ -952,7 +979,8 @@ sparc64_store_arguments (struct regcache valbuf = buf; len = 8; if (element < 16) - regnum = SPARC64_D0_REGNUM + element; + regnum = gdbarch_num_regs (gdbarch) + SPARC64_D0_REGNUM + + element; } } else @@ -969,19 +997,24 @@ sparc64_store_arguments (struct regcache /* If we're storing the value in a floating-point register, also store it in the corresponding %0 register(s). */ - if (regnum >= SPARC64_D0_REGNUM && regnum <= SPARC64_D10_REGNUM) - { - gdb_assert (element < 6); - regnum = SPARC_O0_REGNUM + element; - regcache_cooked_write (regcache, regnum, valbuf); - } - else if (regnum >= SPARC64_Q0_REGNUM && regnum <= SPARC64_Q8_REGNUM) - { - gdb_assert (element < 5); - regnum = SPARC_O0_REGNUM + element; - regcache_cooked_write (regcache, regnum, valbuf); - regcache_cooked_write (regcache, regnum + 1, valbuf + 8); - } + if (regnum >= gdbarch_num_regs (gdbarch)) + { + regnum -= gdbarch_num_regs (gdbarch); + + if (regnum >= SPARC64_D0_REGNUM && regnum <= SPARC64_D10_REGNUM) + { + gdb_assert (element < 6); + regnum = SPARC_O0_REGNUM + element; + regcache_cooked_write (regcache, regnum, valbuf); + } + else if (regnum >= SPARC64_Q0_REGNUM && regnum <= SPARC64_Q8_REGNUM) + { + gdb_assert (element < 5); + regnum = SPARC_O0_REGNUM + element; + regcache_cooked_write (regcache, regnum, valbuf); + regcache_cooked_write (regcache, regnum + 1, valbuf + 8); + } + } } /* Always store the argument in memory. */ @@ -1185,6 +1218,10 @@ sparc64_init_abi (struct gdbarch_info in tdep->pc_regnum = SPARC64_PC_REGNUM; tdep->npc_regnum = SPARC64_NPC_REGNUM; + tdep->fpu_register_names = sparc64_fpu_register_names; + tdep->fpu_registers_num = ARRAY_SIZE (sparc64_fpu_register_names); + tdep->cp0_register_names = sparc64_cp0_register_names; + tdep->cp0_registers_num = ARRAY_SIZE (sparc64_cp0_register_names); /* This is what all the fuss is about. */ set_gdbarch_long_bit (gdbarch, 64);