| Message ID | 1483977924-14522-2-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
On Mon, Jan 9, 2017 at 8:05 AM, Peter Maydell <peter.maydell@linaro.org> wrote: > Augment the GICv3's QOM device interface by adding two > new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to > each CPU. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Thanks, Alistair > --- > include/hw/intc/arm_gicv3_common.h | 2 ++ > hw/intc/arm_gicv3_common.c | 6 ++++++ > 2 files changed, 8 insertions(+) > > diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h > index 341a311..beb2c77 100644 > --- a/include/hw/intc/arm_gicv3_common.h > +++ b/include/hw/intc/arm_gicv3_common.h > @@ -145,6 +145,8 @@ struct GICv3CPUState { > CPUState *cpu; > qemu_irq parent_irq; > qemu_irq parent_fiq; > + qemu_irq parent_virq; > + qemu_irq parent_vfiq; > > /* Redistributor */ > uint32_t level; /* Current IRQ level */ > diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c > index 0aa9b9c..0ee67a4 100644 > --- a/hw/intc/arm_gicv3_common.c > +++ b/hw/intc/arm_gicv3_common.c > @@ -126,6 +126,12 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, > for (i = 0; i < s->num_cpu; i++) { > sysbus_init_irq(sbd, &s->cpu[i].parent_fiq); > } > + for (i = 0; i < s->num_cpu; i++) { > + sysbus_init_irq(sbd, &s->cpu[i].parent_virq); > + } > + for (i = 0; i < s->num_cpu; i++) { > + sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq); > + } > > memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s, > "gicv3_dist", 0x10000); > -- > 2.7.4 > >
diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h index 341a311..beb2c77 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -145,6 +145,8 @@ struct GICv3CPUState { CPUState *cpu; qemu_irq parent_irq; qemu_irq parent_fiq; + qemu_irq parent_virq; + qemu_irq parent_vfiq; /* Redistributor */ uint32_t level; /* Current IRQ level */ diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 0aa9b9c..0ee67a4 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -126,6 +126,12 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, for (i = 0; i < s->num_cpu; i++) { sysbus_init_irq(sbd, &s->cpu[i].parent_fiq); } + for (i = 0; i < s->num_cpu; i++) { + sysbus_init_irq(sbd, &s->cpu[i].parent_virq); + } + for (i = 0; i < s->num_cpu; i++) { + sysbus_init_irq(sbd, &s->cpu[i].parent_vfiq); + } memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s, "gicv3_dist", 0x10000);
Augment the GICv3's QOM device interface by adding two new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to each CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- include/hw/intc/arm_gicv3_common.h | 2 ++ hw/intc/arm_gicv3_common.c | 6 ++++++ 2 files changed, 8 insertions(+) -- 2.7.4