[doc,committed] fix overfull hboxes in GCC manual

Message ID 58754878.3060809@codesourcery.com
State New
Headers show

Commit Message

Sandra Loosemore Jan. 10, 2017, 8:47 p.m.
I've checked in this patch to address various overfull hbox warnings in 
the PDF version of the GCC manual.  These changes are intended to be 
completely boring and content-free.  ;-)

There's still one case, in the ARM -mtune description, that needs more 
thought -- I'm considering changing all such lists to use @gccoptlist 
with a ragged right margin rather than flowed inline text.  That would 
be a fairly mechanical change but it would touch a lot of other sections 
as well, so I thought it better to leave it separate, at least.

-Sandra

Patch hide | download patch | download mbox

Index: gcc/doc/extend.texi
===================================================================
--- gcc/doc/extend.texi	(revision 244215)
+++ gcc/doc/extend.texi	(working copy)
@@ -5943,10 +5943,10 @@  at all.  Just use an appropriate linker
   @{ ...
   @} > text
   /* Leave .rodata in flash and add an offset of 0x4000 to all
-     addresses so that respective objects can be accessed by LD
-     instructions and open coded C/C++.  This means there is no
-     need for progmem in the source and no overhead by read-only
-     data in RAM.  */
+     addresses so that respective objects can be accessed by
+     LD instructions and open coded C/C++.  This means there
+     is no need for progmem in the source and no overhead by
+     read-only data in RAM.  */
   .rodata ADDR(.text) + SIZEOF (.text) + 0x4000 :
   @{
     *(.rodata)
@@ -8687,8 +8687,8 @@  top:
 With no modifiers, this is what the output from the operands would be for the 
 @samp{att} and @samp{intel} dialects of assembler:
 
-@multitable {Operand} {masm=att} {OFFSET FLAT:.L2}
-@headitem Operand @tab masm=att @tab masm=intel
+@multitable {Operand} {$.L2} {OFFSET FLAT:.L2}
+@headitem Operand @tab @samp{att} @tab @samp{intel}
 @item @code{%0}
 @tab @code{%eax}
 @tab @code{eax}
@@ -8702,8 +8702,8 @@  With no modifiers, this is what the outp
 
 The table below shows the list of supported modifiers and their effects.
 
-@multitable {Modifier} {Print the opcode suffix for the size of th} {Operand} {masm=att} {masm=intel}
-@headitem Modifier @tab Description @tab Operand @tab @option{masm=att} @tab @option{masm=intel}
+@multitable {Modifier} {Print the opcode suffix for the size of th} {Operand} {@samp{att}} {@samp{intel}}
+@headitem Modifier @tab Description @tab Operand @tab @samp{att} @tab @samp{intel}
 @item @code{z}
 @tab Print the opcode suffix for the size of the current integer operand (one of @code{b}/@code{w}/@code{l}/@code{q}).
 @tab @code{%z0}
@@ -12727,7 +12727,9 @@  points to.  Counting starts at @code{0}.
 If the address does not point to flash memory, return @code{-1}.
 
 @smallexample
-unsigned char __builtin_avr_insert_bits (unsigned long map, unsigned char bits, unsigned char val)
+unsigned char __builtin_avr_insert_bits (unsigned long map,
+                                         unsigned char bits,
+                                         unsigned char val)
 @end smallexample
 
 @noindent
@@ -18128,13 +18130,16 @@  __vector long long int
 vec_extract_sig (__vector double source);
 
 __vector float
-vec_insert_exp (__vector unsigned int significands,  __vector unsigned int exponents);
+vec_insert_exp (__vector unsigned int significands,
+                __vector unsigned int exponents);
 __vector double
 vec_insert_exp (__vector unsigned long long int significands,
                 __vector unsigned long long int exponents);
 
-__vector int vec_test_data_class (__vector float source, unsigned int condition);
-__vector long long int vec_test_data_class (__vector double source, unsigned int condition);
+__vector int vec_test_data_class (__vector float source,
+                                  unsigned int condition);
+__vector long long int vec_test_data_class (__vector double source,
+                                            unsigned int condition);
 @end smallexample
 
 The @code{vec_extract_sig} and @code{vec_extract_exp} built-in
@@ -18229,9 +18234,9 @@  vector unsigned int __builtin_crypto_vsh
                                                  int, int);
 @end smallexample
 
-The second argument to the @var{__builtin_crypto_vshasigmad} and
-@var{__builtin_crypto_vshasigmaw} builtin functions must be a constant
-integer that is 0 or 1.  The third argument to these builtin functions
+The second argument to @var{__builtin_crypto_vshasigmad} and
+@var{__builtin_crypto_vshasigmaw} must be a constant
+integer that is 0 or 1.  The third argument to these built-in functions
 must be a constant integer in the range of 0 to 15.
 
 If the ISA 3.0 instruction set additions 
@@ -20454,8 +20459,10 @@  void __builtin_ia32_xsaveopt64 (void *,
 The following built-in functions are available when @option{-mtbm} is used.
 Both of them generate the immediate form of the bextr machine instruction.
 @smallexample
-unsigned int __builtin_ia32_bextri_u32 (unsigned int, const unsigned int);
-unsigned long long __builtin_ia32_bextri_u64 (unsigned long long, const unsigned long long);
+unsigned int __builtin_ia32_bextri_u32 (unsigned int,
+                                        const unsigned int);
+unsigned long long __builtin_ia32_bextri_u64 (unsigned long long,
+                                              const unsigned long long);
 @end smallexample
 
 
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi	(revision 244216)
+++ gcc/doc/invoke.texi	(working copy)
@@ -3420,8 +3420,8 @@  for 88-color and 256-color modes backgro
 
 The default @env{GCC_COLORS} is
 @smallexample
-error=01;31:warning=01;35:note=01;36:range1=32:range2=34:locus=01:quote=01:\
-fixit-insert=32:fixit-delete=31:\
+error=01;31:warning=01;35:note=01;36:range1=32:range2=34:locus=01:\
+quote=01:fixit-insert=32:fixit-delete=31:\
 diff-filename=01:diff-hunk=32:diff-delete=31:diff-insert=32
 @end smallexample
 @noindent
@@ -3740,7 +3740,7 @@  Options} and @ref{Objective-C and Object
 -Wimplicit-int @r{(C and Objective-C only)} @gol
 -Wimplicit-function-declaration @r{(C and Objective-C only)} @gol
 -Winit-self @r{(only for C++)} @gol
--Wlogical-not-parentheses
+-Wlogical-not-parentheses @gol
 -Wmain @r{(only for C/ObjC and unless} @option{-ffreestanding}@r{)}  @gol
 -Wmaybe-uninitialized @gol
 -Wmemset-elt-size @gol
@@ -10917,14 +10917,11 @@  ThreadSanitizer and UndefinedBehaviorSan
 AddressSanitizer is @code{halt_on_error=1}. This can be overridden through
 setting the @code{halt_on_error} flag in the corresponding environment variable.
 
-Syntax without explicit @var{opts} parameter is deprecated.  It is equivalent to
-@smallexample
--fsanitize-recover=undefined,float-cast-overflow,float-divide-by-zero,bounds-strict
-@end smallexample
-@noindent
-Similarly @option{-fno-sanitize-recover} is equivalent to
+Syntax without an explicit @var{opts} parameter is deprecated.  It is
+equivalent to specifying an @var{opts} list of:
+
 @smallexample
--fno-sanitize-recover=undefined,float-cast-overflow,float-divide-by-zero,bounds-strict
+undefined,float-cast-overflow,float-divide-by-zero,bounds-strict
 @end smallexample
 
 @item -fsanitize-address-use-after-scope
Index: gcc/doc/md.texi
===================================================================
--- gcc/doc/md.texi	(revision 244215)
+++ gcc/doc/md.texi	(working copy)
@@ -2997,7 +2997,7 @@  Floating point register (containing 32-b
 Altivec vector register
 
 @item wa
-Any VSX register if the -mvsx option was used or NO_REGS.
+Any VSX register if the @option{-mvsx} option was used or NO_REGS.
 
 When using any of the register constraints (@code{wa}, @code{wd},
 @code{wf}, @code{wg}, @code{wh}, @code{wi}, @code{wj}, @code{wk},
@@ -3010,31 +3010,43 @@  is an operand of a VSX instruction that
 numbering.
 
 @smallexample
-asm ("xvadddp %x0,%x1,%x2" : "=wa" (v1) : "wa" (v2), "wa" (v3));
+asm ("xvadddp %x0,%x1,%x2"
+     : "=wa" (v1)
+     : "wa" (v2), "wa" (v3));
 @end smallexample
 
+@noindent
 is correct, but:
 
 @smallexample
-asm ("xvadddp %0,%1,%2" : "=wa" (v1) : "wa" (v2), "wa" (v3));
+asm ("xvadddp %0,%1,%2" 
+     : "=wa" (v1) 
+     : "wa" (v2), "wa" (v3));
 @end smallexample
 
+@noindent
 is not correct.
 
 If an instruction only takes Altivec registers, you do not want to use
 @code{%x<n>}.
 
 @smallexample
-asm ("xsaddqp %0,%1,%2" : "=v" (v1) : "v" (v2), "v" (v3));
+asm ("xsaddqp %0,%1,%2"
+     : "=v" (v1)
+     : "v" (v2), "v" (v3));
 @end smallexample
 
+@noindent
 is correct because the @code{xsaddqp} instruction only takes Altivec
 registers, while:
 
 @smallexample
-asm ("xsaddqp %x0,%x1,%x2" : "=v" (v1) : "v" (v2), "v" (v3));
+asm ("xsaddqp %x0,%x1,%x2" 
+     : "=v" (v1) 
+     : "v" (v2), "v" (v3));
 @end smallexample
 
+@noindent
 is incorrect.
 
 @item wb
Index: gcc/doc/objc.texi
===================================================================
--- gcc/doc/objc.texi	(revision 244215)
+++ gcc/doc/objc.texi	(working copy)
@@ -381,7 +381,7 @@  compiler on an i386 machine:
 
 @sp 1
 
-@multitable @columnfractions .25 .75
+@multitable @columnfractions .60 .40
 @item Objective-C type
 @tab Compiler encoding
 @item
@@ -404,7 +404,7 @@  struct @{
 @smallexample
 int a __attribute__ ((vector_size (16)));
 @end smallexample
-@tab @code{![16,16i]} (alignment would depend on the machine)
+@tab @code{![16,16i]} (alignment depends on the machine)
 @end multitable
 
 @sp 1