From patchwork Sat Jan 14 19:16:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 91512 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp746523qgi; Sat, 14 Jan 2017 11:16:32 -0800 (PST) X-Received: by 10.84.229.72 with SMTP id d8mr16697880pln.21.1484421392426; Sat, 14 Jan 2017 11:16:32 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id x124si16453062pfx.67.2017.01.14.11.16.32 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 14 Jan 2017 11:16:32 -0800 (PST) Received-SPF: pass (google.com: domain of gdb-patches-return-136219-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org; spf=pass (google.com: domain of gdb-patches-return-136219-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gdb-patches-return-136219-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :cc:content-type; q=dns; s=default; b=h80cFLYUcI5Qit/LJ99Sf0HVQ3 DDNkOV+7M8wCYzWEAsuu+QfskJyYN7NznmB7Lrbb9umvBYilXOA4HlmAzAUSleDf 2jI7cy9xJZ7YR4t1u1TyCOl2H2rhYM43Cy9dXqE99V+neTZxgTxwZovJQItW4mlL weuAlT/r0JnucpL00= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :cc:content-type; s=default; bh=n32PXxsu2nO+BjDP6IRZKIX+9qM=; b= WmLeTsOyEJrBWWD6/2TJcN1iJHvjMGEe3bDxSvBvSV04yPazSxejtM8J7DI9yN62 e0/xj5b8dc1GRGDfrH4jLweOfGgT7Y06HHpnvqU5YzXE9eYfPR/z3mGwfgZHxkTG GiRlghowBuOlcGXW/m2OaaxehJJral4LcQMPBe9qVGs= Received: (qmail 93532 invoked by alias); 14 Jan 2017 19:16:25 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 91196 invoked by uid 89); 14 Jan 2017 19:16:23 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy=1, 50, reserved X-HELO: mail-yb0-f171.google.com Received: from mail-yb0-f171.google.com (HELO mail-yb0-f171.google.com) (209.85.213.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 14 Jan 2017 19:16:13 +0000 Received: by mail-yb0-f171.google.com with SMTP id w194so20385978ybe.0 for ; Sat, 14 Jan 2017 11:16:13 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=1td886As8ssLGKj6Fd8WwZ6pOloPbTV6mRUAtOlZUjE=; b=d9PaJicmRqdUWja7Pcni92OVSTqQYGOioMGdlkG1u96kGNtIe2dHkU3FX3qzREvz6x PNs9ecQ6PwNiBA0QvHWcMEy7aTRuMtedz6FGnVNIIlBtkg8qresBpWlWFOAXtGfdCL6E VmYuFBVBqSKfcBWCm0wwqBNgzvx48cQj7j6hKd9aq2+KCzIMgFM9Q9g0Q0jMneIZyX2S benp4reJ12tGgtAE4JsDw38+VAWvS19iNSxWNWMbCF4Xm74J2iAJfjBUA/wGbe71jH+w 2tFXm/o/qPbg3hgO945hmP6nNDRuotg5YRGWY22QZeirMjFCBf3uI4/RCJlZ3StwxbRJ 3yZA== X-Gm-Message-State: AIkVDXI1sSsSXS/RipPzACKCULV8ksSMPpMkdgG4rCwb3eRzMtcN7bAq09lwU/Tf3eLt87bOnAqo3GoI8hHMuPHo X-Received: by 10.37.170.225 with SMTP id t88mr9021627ybi.74.1484421371862; Sat, 14 Jan 2017 11:16:11 -0800 (PST) MIME-Version: 1.0 Received: by 10.129.92.4 with HTTP; Sat, 14 Jan 2017 11:16:11 -0800 (PST) From: Jim Wilson Date: Sat, 14 Jan 2017 11:16:11 -0800 Message-ID: Subject: [PATCH] aarch64 sim addv bug fix To: gdb-patches@sourceware.org Cc: Nick Clifton The addv instruction is storing results to general registers instead of vector registers. The reserved instruction check is wrong, It should be not full in case 2, and unconditionally in case 3. The testcase fails without the patch, and works with the patch. The patch reduces gcc C testsuite failures from 2227 to 2174 (-57). Jim sim/aarch64/ * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In case 3, call HALT_UNALLOC unconditionally. sim/testsuite/sim/aarch64/ * addv.s: New. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index 36129e5..6237c09 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -3445,28 +3445,25 @@ do_vec_ADDV (sim_cpu *cpu) case 0: for (i = 0; i < (full ? 16 : 8); i++) val += aarch64_get_vec_u8 (cpu, vm, i); - aarch64_set_reg_u64 (cpu, rd, NO_SP, val); + aarch64_set_vec_u64 (cpu, rd, 0, val); return; case 1: for (i = 0; i < (full ? 8 : 4); i++) val += aarch64_get_vec_u16 (cpu, vm, i); - aarch64_set_reg_u64 (cpu, rd, NO_SP, val); + aarch64_set_vec_u64 (cpu, rd, 0, val); return; case 2: - for (i = 0; i < (full ? 4 : 2); i++) + if (! full) + HALT_UNALLOC; + for (i = 0; i < 4; i++) val += aarch64_get_vec_u32 (cpu, vm, i); - aarch64_set_reg_u64 (cpu, rd, NO_SP, val); + aarch64_set_vec_u64 (cpu, rd, 0, val); return; case 3: - if (! full) - HALT_UNALLOC; - val = aarch64_get_vec_u64 (cpu, vm, 0); - val += aarch64_get_vec_u64 (cpu, vm, 1); - aarch64_set_reg_u64 (cpu, rd, NO_SP, val); - return; + HALT_UNALLOC; } } diff --git a/sim/testsuite/sim/aarch64/addv.s b/sim/testsuite/sim/aarch64/addv.s new file mode 100644 index 0000000..4da8935 --- /dev/null +++ b/sim/testsuite/sim/aarch64/addv.s @@ -0,0 +1,50 @@ +# mach: aarch64 + +# Check the add across vector instruction: addv. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d + + start + adrp x0, input + ldr q0, [x0, #:lo12:input] + + addv b1, v0.8b + mov x1, v1.d[0] + cmp x1, #36 + bne .Lfailure + + addv b1, v0.16b + mov x1, v1.d[0] + cmp x1, #136 + bne .Lfailure + + addv h1, v0.4h + mov x1, v1.d[0] + mov x2, #5136 + cmp x1, x2 + bne .Lfailure + + addv h1, v0.8h + mov x1, v1.d[0] + mov x2, #18496 + cmp x1, x2 + bne .Lfailure + + addv s1, v0.4s + mov x1, v1.d[0] + mov x2, 8220 + movk x2, 0x2824, lsl 16 + cmp x1, x2 + bne .Lfailure + + pass +.Lfailure: + fail