[1/8,V2] EXYNOS: CLK: Add i2c clock

Message ID 1339049394-4816-2-git-send-email-rajeshwari.s@samsung.com
State New
Headers show

Commit Message

Rajeshwari Shinde June 7, 2012, 6:09 a.m.
This adds i2c clock information for EXYNOS5.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
---
changes in V2:
	- Incorporated comments from Simon Glass which are removed extra 
	braces around (readl(&clk->div_top1)) >> 24 and	gave a tab space for 
	return statement.
 arch/arm/cpu/armv7/exynos/clock.c      |   33 ++++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-exynos/clk.h |    1 +
 2 files changed, 34 insertions(+), 0 deletions(-)

Comments

Simon Glass June 12, 2012, 5:46 a.m. | #1
On Wed, Jun 6, 2012 at 11:09 PM, Rajeshwari Shinde <rajeshwari.s@samsung.com
> wrote:

> This adds i2c clock information for EXYNOS5.
>
> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
> Signed-off-by: Doug Anderson <dianders@chromium.org>
> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
> Acked-by: Simon Glass <sjg@chromium.org>
> ---
> changes in V2:
>        - Incorporated comments from Simon Glass which are removed extra
>        braces around (readl(&clk->div_top1)) >> 24 and gave a tab space for
>        return statement.
>

Acked-by: Simon Glass <sjg@chromium.org>


>  arch/arm/cpu/armv7/exynos/clock.c      |   33
> ++++++++++++++++++++++++++++++++
>  arch/arm/include/asm/arch-exynos/clk.h |    1 +
>  2 files changed, 34 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/exynos/clock.c
> b/arch/arm/cpu/armv7/exynos/clock.c
> index 330bd75..a80928b 100644
> --- a/arch/arm/cpu/armv7/exynos/clock.c
> +++ b/arch/arm/cpu/armv7/exynos/clock.c
> @@ -578,6 +578,29 @@ void exynos4_set_mipi_clk(void)
>        writel(cfg, &clk->div_lcd0);
>  }
>
> +/*
> + * I2C
> + *
> + * exynos5: obtaining the I2C clock
> + */
> +static unsigned long exynos5_get_i2c_clk(void)
> +{
> +       struct exynos5_clock *clk =
> +               (struct exynos5_clock *)samsung_get_base_clock();
> +       unsigned long aclk_66, aclk_66_pre, sclk;
> +       unsigned int ratio;
> +
> +       sclk = get_pll_clk(MPLL);
> +
> +       ratio = (readl(&clk->div_top1)) >> 24;
> +       ratio &= (0x7);
> +       aclk_66_pre = sclk/(ratio+1);
> +       ratio = readl(&clk->div_top0);
> +       ratio &= (0x7);
> +       aclk_66 = aclk_66_pre/(ratio+1);
> +       return aclk_66;
> +}
> +
>  unsigned long get_pll_clk(int pllreg)
>  {
>        if (cpu_is_exynos5())
> @@ -594,6 +617,16 @@ unsigned long get_arm_clk(void)
>                return exynos4_get_arm_clk();
>  }
>
> +unsigned long get_i2c_clk(void)
> +{
> +       if (cpu_is_exynos5()) {
> +               return exynos5_get_i2c_clk();
> +       } else {
> +               debug("I2C clock is not set for this CPU\n");
> +               return 0;
> +       }
> +}
> +
>  unsigned long get_pwm_clk(void)
>  {
>        if (cpu_is_exynos5())
> diff --git a/arch/arm/include/asm/arch-exynos/clk.h
> b/arch/arm/include/asm/arch-exynos/clk.h
> index 637fb4b..72dc655 100644
> --- a/arch/arm/include/asm/arch-exynos/clk.h
> +++ b/arch/arm/include/asm/arch-exynos/clk.h
> @@ -30,6 +30,7 @@
>
>  unsigned long get_pll_clk(int pllreg);
>  unsigned long get_arm_clk(void);
> +unsigned long get_i2c_clk(void);
>  unsigned long get_pwm_clk(void);
>  unsigned long get_uart_clk(int dev_index);
>  void set_mmc_clk(int dev_index, unsigned int div);
> --
> 1.7.4.4
>
>

Patch

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 330bd75..a80928b 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -578,6 +578,29 @@  void exynos4_set_mipi_clk(void)
 	writel(cfg, &clk->div_lcd0);
 }
 
+/*
+ * I2C
+ *
+ * exynos5: obtaining the I2C clock
+ */
+static unsigned long exynos5_get_i2c_clk(void)
+{
+	struct exynos5_clock *clk =
+		(struct exynos5_clock *)samsung_get_base_clock();
+	unsigned long aclk_66, aclk_66_pre, sclk;
+	unsigned int ratio;
+
+	sclk = get_pll_clk(MPLL);
+
+	ratio = (readl(&clk->div_top1)) >> 24;
+	ratio &= (0x7);
+	aclk_66_pre = sclk/(ratio+1);
+	ratio = readl(&clk->div_top0);
+	ratio &= (0x7);
+	aclk_66 = aclk_66_pre/(ratio+1);
+	return aclk_66;
+}
+
 unsigned long get_pll_clk(int pllreg)
 {
 	if (cpu_is_exynos5())
@@ -594,6 +617,16 @@  unsigned long get_arm_clk(void)
 		return exynos4_get_arm_clk();
 }
 
+unsigned long get_i2c_clk(void)
+{
+	if (cpu_is_exynos5()) {
+		return exynos5_get_i2c_clk();
+	} else {
+		debug("I2C clock is not set for this CPU\n");
+		return 0;
+	}
+}
+
 unsigned long get_pwm_clk(void)
 {
 	if (cpu_is_exynos5())
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index 637fb4b..72dc655 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -30,6 +30,7 @@ 
 
 unsigned long get_pll_clk(int pllreg);
 unsigned long get_arm_clk(void);
+unsigned long get_i2c_clk(void);
 unsigned long get_pwm_clk(void);
 unsigned long get_uart_clk(int dev_index);
 void set_mmc_clk(int dev_index, unsigned int div);