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[65.50.211.133]) by mx.google.com with ESMTPS id v123si4433191qkh.281.2017.01.20.00.46.22 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Jan 2017 00:46:22 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 65.50.211.133 as permitted sender) client-ip=65.50.211.133; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 65.50.211.133 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cUUpv-0001yu-Qw; Fri, 20 Jan 2017 08:46:19 +0000 Received: from mail-pf0-f174.google.com ([209.85.192.174]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cUUpg-0001BY-0G for linux-arm-kernel@lists.infradead.org; Fri, 20 Jan 2017 08:46:09 +0000 Received: by mail-pf0-f174.google.com with SMTP id e4so20957429pfg.1 for ; Fri, 20 Jan 2017 00:45:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pLdjYjM/pU76Bucqi9qLpMxaaV2CntVUOQW7hFyuRNw=; b=Ultj3Gb6Nfpb2GF06qycvYIuoqHi/NKxfGnNCO/fxO+zoC6uXfNAO9dKs52mWPOTKC rdQGPg4cji8xGY9b5693HvzVp7xBx3ENCuCnALawkzCxp1T+lxQdfdr66rbZw6XTG+oY +dFC6mZjOX2uHkBQnOGUYY7cNWmc683qh7RcA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pLdjYjM/pU76Bucqi9qLpMxaaV2CntVUOQW7hFyuRNw=; b=uJl00VjCwFqJmYwa6Ff2lRLBe6qncrumxYbOgJKj07YMBWyBVJDbRWloQytc644uC0 9kZWcvT67rAmMxIgj+09CmBc6c7/f/1uS/bGd8waSIZxX6aEKv/7TdOCrX368VXQegUI KjbyJufVTr031nzZBm0K6Mf1hKqgyr+fRRswGNckWlTHT5VgZCDOnhzFEp9eUpCaxI0X 4berpjQq5fK3158ZMiZQa1X5GIDXUZ7Ddbqr4lrsJ4dWWdj8p9Iq5GhmcRXzGE6YHmFZ vSrTB/QQiQRlwdbCqbpvvddv/79Yxqgd/9vHZjLNsdzr2TGKf6xSdHtjwwbOTlHYHx4Z oi9Q== X-Gm-Message-State: AIkVDXI42i9tLui/bE2anfhpyk1UczO4xn9AI97OrsQ2WZ34NntmHzFI/kfbOkQRyvh9i6LA X-Received: by 10.98.48.134 with SMTP id w128mr15113627pfw.133.1484901883068; Fri, 20 Jan 2017 00:44:43 -0800 (PST) Received: from localhost.localdomain ([104.237.91.89]) by smtp.gmail.com with ESMTPSA id 16sm14575255pfk.54.2017.01.20.00.44.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 20 Jan 2017 00:44:42 -0800 (PST) From: Baoyou Xie To: jun.nie@linaro.org, wsa@the-dreams.de, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCH v1 3/3] i2c: zx2967: add i2c controller driver for ZTE's zx2967 family Date: Fri, 20 Jan 2017 16:43:47 +0800 Message-Id: <1484901827-16369-3-git-send-email-baoyou.xie@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1484901827-16369-1-git-send-email-baoyou.xie@linaro.org> References: <1484901827-16369-1-git-send-email-baoyou.xie@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170120_004604_351043_CBC33A1C X-CRM114-Status: GOOD ( 20.75 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.5 RCVD_IN_SORBS_SPAM RBL: SORBS: sender is a spam source [209.85.192.174 listed in dnsbl.sorbs.net] -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [209.85.192.174 listed in list.dnswl.org] -1.2 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.192.174 listed in wl.mailspike.net] 0.0 HK_RANDOM_ENVFROM Envelope sender username looks random -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, xie.baoyou@zte.com.cn, linux-kernel@vger.kernel.org, chen.chaokai@zte.com.cn, linux-i2c@vger.kernel.org, wang.qiang01@zte.com.cn, baoyou.xie@linaro.org, shawnguo@kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org This patch adds i2c controller driver for ZTE's zx2967 family. Signed-off-by: Baoyou Xie --- drivers/i2c/busses/Kconfig | 8 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-zx2967.c | 645 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 654 insertions(+) create mode 100644 drivers/i2c/busses/i2c-zx2967.c -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index e4a603e..946d2b0 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -1246,4 +1246,12 @@ config I2C_OPAL This driver can also be built as a module. If so, the module will be called as i2c-opal. +config I2C_ZX2967 + bool "ZTE zx2967 I2C support" + depends on ARCH_ZX + default y + help + Selecting this option will add ZX I2C driver. + If unsure, say y. + endmenu diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index beb4809..16b2901 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -101,6 +101,7 @@ obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o obj-$(CONFIG_I2C_XLR) += i2c-xlr.o obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o +obj-$(CONFIG_I2C_ZX2967) += i2c-zx2967.o # External I2C/SMBus adapter drivers obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o diff --git a/drivers/i2c/busses/i2c-zx2967.c b/drivers/i2c/busses/i2c-zx2967.c new file mode 100644 index 0000000..6c2145b --- /dev/null +++ b/drivers/i2c/busses/i2c-zx2967.c @@ -0,0 +1,645 @@ +/* + * ZTE's zx2967 family i2c bus controller driver + * + * Copyright (C) 2017 ZTE Ltd. + * + * Author: Baoyou Xie + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define BW1 (u32)1 + +#define REG_CMD 0x04 +#define REG_DEVADDR_H 0x0C +#define REG_DEVADDR_L 0x10 +#define REG_CLK_DIV_FS 0x14 +#define REG_CLK_DIV_HS 0x18 +#define REG_WRCONF 0x1C +#define REG_RDCONF 0x20 +#define REG_DATA 0x24 +#define REG_STAT 0x28 + +#define I2C_STOP 0 +#define I2C_MASTER (1 << 0) +#define I2C_ADDR_MODE_TEN (1 << 1) +#define I2C_IRQ_MSK_ENABLE (1 << 3) +#define I2C_RW_READ (1 << 4) +#define I2C_CMB_RW_EN (1 << 5) +#define I2C_START (1 << 6) +#define I2C_ADDR_MODE_TEN (1 << 1) + +#define I2C_WFIFO_RESET (1 << 7) +#define I2C_RFIFO_RESET (1 << 7) + +#define I2C_IRQ_ACK_CLEAR (1 << 7) +#define I2C_INT_MASK 0x3f + +#define I2C_TRANS_DONE (1 << 0) +#define I2C_ERROR_DEVICE (1 << 1) +#define I2C_ERROR_DATA (1 << 2) +#define I2C_ERROR_MASK (I2C_ERROR_DATA | I2C_ERROR_DEVICE) + +#define I2C_SR_BUSY (1 << 6) + +#define I2C_SR_EDEVICE (1 << 1) +#define I2C_SR_EDATA (1 << 2) + +#define I2C_FIFO_MAX 16 + +#define I2C_TIMEOUT msecs_to_jiffies(1000) + +struct zx2967_i2c_info { + spinlock_t lock; + struct device *dev; + struct i2c_adapter adap; + struct clk *clk; + struct completion complete; + u32 clk_freq; + struct pinctrl *pin_scl; + struct pinctrl *pin_sda; + void __iomem *reg_base; + size_t residue; + int id; + int irq; + int msg_rd; + u8 *buf; + u8 access_cnt; + bool is_suspended; +}; + +static void zx2967_i2c_writel(struct zx2967_i2c_info *zx_i2c, + u32 val, unsigned long reg) +{ + writel_relaxed(val, zx_i2c->reg_base + reg); +} + +static u32 zx2967_i2c_readl(struct zx2967_i2c_info *zx_i2c, unsigned long reg) +{ + return readl_relaxed(zx_i2c->reg_base + reg); +} + +static void zx2967_i2c_writesb(struct zx2967_i2c_info *zx_i2c, + void *data, unsigned long reg, int len) +{ + writesb(zx_i2c->reg_base + reg, data, len); +} + +static void zx2967_i2c_readsb(struct zx2967_i2c_info *zx_i2c, + void *data, unsigned long reg, int len) +{ + readsb(zx_i2c->reg_base + reg, data, len); +} + +static void zx2967_i2c_start_ctrl(struct zx2967_i2c_info *zx_i2c) +{ + u32 status; + u32 ctl; + + status = zx2967_i2c_readl(zx_i2c, REG_STAT); + status |= I2C_IRQ_ACK_CLEAR; + zx2967_i2c_writel(zx_i2c, status, REG_STAT); + + ctl = zx2967_i2c_readl(zx_i2c, REG_CMD); + if (zx_i2c->msg_rd) + ctl |= I2C_RW_READ; + else + ctl &= ~I2C_RW_READ; + ctl &= ~I2C_CMB_RW_EN; + ctl |= I2C_START; + zx2967_i2c_writel(zx_i2c, ctl, REG_CMD); +} + +static int zx2967_i2c_flush_fifos(struct zx2967_i2c_info *zx_i2c) +{ + u32 val = 0; + u32 offset = 0; + + if (zx_i2c->msg_rd) { + offset = REG_RDCONF; + val = I2C_RFIFO_RESET; + } else { + offset = REG_WRCONF; + val = I2C_WFIFO_RESET; + } + + val |= zx2967_i2c_readl(zx_i2c, offset); + zx2967_i2c_writel(zx_i2c, val, offset); + + return 0; +} + +static int zx2967_i2c_empty_rx_fifo(struct zx2967_i2c_info *zx_i2c, u32 size) +{ + u8 val[I2C_FIFO_MAX] = {0}; + int i = 0; + + if (size == 0) { + dev_err(zx_i2c->dev, "size is invalid\n"); + return -EINVAL; + } + + zx2967_i2c_readsb(zx_i2c, val, REG_DATA, size); + for (i = 0; i < size; i++) { + *(zx_i2c->buf++) = val[i]; + zx_i2c->residue--; + if (zx_i2c->residue <= 0) + break; + } + + barrier(); + + return 0; +} + +static int zx2967_i2c_fill_tx_fifo(struct zx2967_i2c_info *zx_i2c) +{ + u8 *buf = zx_i2c->buf; + size_t residue = zx_i2c->residue; + + if (residue == 0) { + dev_err(zx_i2c->dev, "residue is %d\n", (int)residue); + return -EINVAL; + } + + if (residue <= I2C_FIFO_MAX) { + zx2967_i2c_writesb(zx_i2c, buf, REG_DATA, residue); + + /* Again update before writing to FIFO to make sure isr sees. */ + zx_i2c->residue = 0; + zx_i2c->buf = NULL; + } else { + zx2967_i2c_writesb(zx_i2c, buf, REG_DATA, I2C_FIFO_MAX); + zx_i2c->residue -= I2C_FIFO_MAX; + zx_i2c->buf += I2C_FIFO_MAX; + } + + barrier(); + + return 0; +} + +static int zx2967_i2c_reset_hardware(struct zx2967_i2c_info *zx_i2c) +{ + u32 val; + u32 clk_div; + u32 status; + + val = I2C_MASTER | I2C_IRQ_MSK_ENABLE; + zx2967_i2c_writel(zx_i2c, val, REG_CMD); + + clk_div = clk_get_rate(zx_i2c->clk) / zx_i2c->clk_freq - 1; + zx2967_i2c_writel(zx_i2c, clk_div, REG_CLK_DIV_FS); + zx2967_i2c_writel(zx_i2c, clk_div, REG_CLK_DIV_HS); + + zx2967_i2c_writel(zx_i2c, I2C_FIFO_MAX - 1, REG_WRCONF); + zx2967_i2c_writel(zx_i2c, I2C_FIFO_MAX - 1, REG_RDCONF); + zx2967_i2c_writel(zx_i2c, 1, REG_RDCONF); + + if (zx2967_i2c_flush_fifos(zx_i2c)) + return -ETIMEDOUT; + + status = zx2967_i2c_readl(zx_i2c, REG_STAT); + if (status & (I2C_SR_BUSY)) + return -EBUSY; + if (status & (I2C_SR_EDEVICE | I2C_SR_EDATA)) + return -EIO; + + enable_irq(zx_i2c->irq); + + return 0; +} + +static void zx2967_i2c_isr_clr(struct zx2967_i2c_info *zx_i2c) +{ + u32 status; + + status = zx2967_i2c_readl(zx_i2c, REG_STAT); + status |= I2C_IRQ_ACK_CLEAR; + zx2967_i2c_writel(zx_i2c, status, REG_STAT); +} + +static irqreturn_t zx2967_i2c_isr(int irq, void *dev_id) +{ + u32 status; + struct zx2967_i2c_info *zx_i2c = (struct zx2967_i2c_info *)dev_id; + unsigned long flags; + + spin_lock_irqsave(&zx_i2c->lock, flags); + + status = zx2967_i2c_readl(zx_i2c, REG_STAT) & I2C_INT_MASK; + zx2967_i2c_isr_clr(zx_i2c); + + if (status & I2C_ERROR_MASK) { + spin_unlock_irqrestore(&zx_i2c->lock, flags); + return IRQ_HANDLED; + } + + if (status & I2C_TRANS_DONE) + complete(&zx_i2c->complete); + + spin_unlock_irqrestore(&zx_i2c->lock, flags); + + return IRQ_HANDLED; +} + +static void zx2967_enable_tenbit(struct zx2967_i2c_info *zx_i2c, __u16 addr) +{ + u16 val = ((addr >> 7) & 0x7); + + if (val > 0) { + zx2967_i2c_writel(zx_i2c, val, REG_DEVADDR_H); + val = (zx2967_i2c_readl(zx_i2c, REG_CMD)) | I2C_ADDR_MODE_TEN; + zx2967_i2c_writel(zx_i2c, val, REG_CMD); + } +} + +static int zx2967_i2c_xfer_msg(struct zx2967_i2c_info *zx_i2c, + struct i2c_msg *msg) +{ + unsigned long time_left = 0; + unsigned int i = 0; + + if (msg->len == 0) + return -EINVAL; + + zx2967_i2c_flush_fifos(zx_i2c); + + zx_i2c->buf = msg->buf; + zx_i2c->residue = msg->len; + zx_i2c->access_cnt = msg->len / I2C_FIFO_MAX; + zx_i2c->msg_rd = (msg->flags & I2C_M_RD); + + if (zx_i2c->msg_rd) { + for (i = 0; i < zx_i2c->access_cnt; i++) { + reinit_completion(&zx_i2c->complete); + zx2967_i2c_writel(zx_i2c, I2C_FIFO_MAX - 1, + REG_RDCONF); + zx2967_i2c_start_ctrl(zx_i2c); + + time_left = wait_for_completion_timeout( + &zx_i2c->complete, I2C_TIMEOUT); + if (time_left == 0) { + dev_err(zx_i2c->dev, + "read i2c transfer timed out\n"); + disable_irq(zx_i2c->irq); + zx2967_i2c_reset_hardware(zx_i2c); + return -EIO; + } + + zx2967_i2c_empty_rx_fifo(zx_i2c, I2C_FIFO_MAX); + } + + if (zx_i2c->residue < I2C_FIFO_MAX) { + reinit_completion(&zx_i2c->complete); + zx2967_i2c_writel(zx_i2c, zx_i2c->residue - 1, + REG_RDCONF); + zx2967_i2c_start_ctrl(zx_i2c); + time_left = wait_for_completion_timeout( + &zx_i2c->complete, I2C_TIMEOUT); + if (time_left == 0) { + dev_err(zx_i2c->dev, + "read i2c transfer timed out\n"); + disable_irq(zx_i2c->irq); + zx2967_i2c_reset_hardware(zx_i2c); + return -EIO; + } + + zx2967_i2c_empty_rx_fifo(zx_i2c, zx_i2c->residue); + } + + zx_i2c->residue = 0; + zx_i2c->access_cnt = 0; + } else { + reinit_completion(&zx_i2c->complete); + zx2967_i2c_fill_tx_fifo(zx_i2c); + zx2967_i2c_start_ctrl(zx_i2c); + + for (i = 0; i < zx_i2c->access_cnt; i++) { + time_left = wait_for_completion_timeout( + &zx_i2c->complete, I2C_TIMEOUT); + if (time_left == 0) { + dev_err(zx_i2c->dev, + "write i2c transfer timed out\n"); + disable_irq(zx_i2c->irq); + zx2967_i2c_reset_hardware(zx_i2c); + return -EIO; + } + + if (zx_i2c->residue != 0) { + reinit_completion(&zx_i2c->complete); + zx2967_i2c_fill_tx_fifo(zx_i2c); + zx2967_i2c_start_ctrl(zx_i2c); + } + } + } + + return 0; +} + +static int zx2967_i2c_xfer(struct i2c_adapter *adap, + struct i2c_msg *msgs, int num) +{ + int i; + int ret = 0; + struct zx2967_i2c_info *zx_i2c = i2c_get_adapdata(adap); + + if (zx_i2c->is_suspended) + return -EBUSY; + + zx2967_i2c_writel(zx_i2c, (msgs->addr & 0x7f), REG_DEVADDR_L); + zx2967_i2c_writel(zx_i2c, (msgs->addr >> 7) & 0x7, REG_DEVADDR_H); + if (zx2967_i2c_readl(zx_i2c, REG_DEVADDR_H) > 0) + zx2967_enable_tenbit(zx_i2c, msgs->addr); + + for (i = 0; i < num; i++) { + ret = zx2967_i2c_xfer_msg(zx_i2c, &msgs[i]); + if (num > 1) + usleep_range(1000, 2000); + if (ret) + break; + } + + return ret ?: i; +} + +static int zx2967_smbus_xfer(struct i2c_adapter *adap, u16 addr, + unsigned short flags, char read_write, + u8 command, int size, union i2c_smbus_data *data) +{ + struct zx2967_i2c_info *zx_i2c = i2c_get_adapdata(adap); + u32 val; + u8 buf[2]; + unsigned long time_left; + + val = zx2967_i2c_readl(zx_i2c, REG_RDCONF); + val |= I2C_RFIFO_RESET; + zx2967_i2c_writel(zx_i2c, val, REG_RDCONF); + zx2967_i2c_writel(zx_i2c, (addr & 0x7f), REG_DEVADDR_L); + + zx2967_enable_tenbit(zx_i2c, addr); + val = zx2967_i2c_readl(zx_i2c, REG_CMD); + val &= ~I2C_RW_READ; + zx2967_i2c_writel(zx_i2c, val, REG_CMD); + + switch (size) { + case I2C_SMBUS_QUICK: + read_write = I2C_SMBUS_WRITE; + break; + case I2C_SMBUS_BYTE: + zx2967_i2c_writel(zx_i2c, command, REG_DATA); + break; + case I2C_SMBUS_BYTE_DATA: + zx2967_i2c_writel(zx_i2c, command, REG_DATA); + + if (read_write == I2C_SMBUS_WRITE) + zx2967_i2c_writel(zx_i2c, data->byte, REG_DATA); + + break; + case I2C_SMBUS_WORD_DATA: + zx2967_i2c_writel(zx_i2c, command, REG_DATA); + zx2967_i2c_writel(zx_i2c, (data->word & 0xff), REG_DATA); + + if (read_write == I2C_SMBUS_WRITE) { + zx2967_i2c_writel(zx_i2c, (data->word >> 8), REG_DATA); + zx2967_i2c_writel(zx_i2c, + (data->word & 0xff), REG_DATA); + } + break; + + default: + dev_warn(&adap->dev, "Unsupported transaction %d\n", size); + return -EOPNOTSUPP; + } + + if (read_write == I2C_SMBUS_WRITE) { + reinit_completion(&zx_i2c->complete); + val = zx2967_i2c_readl(zx_i2c, REG_CMD); + val |= I2C_START; + zx2967_i2c_writel(zx_i2c, val, REG_CMD); + + time_left = wait_for_completion_timeout( + &zx_i2c->complete, I2C_TIMEOUT); + if (time_left == 0) { + dev_err(zx_i2c->dev, "i2c write transfer timed out\n"); + disable_irq(zx_i2c->irq); + zx2967_i2c_reset_hardware(zx_i2c); + return -EIO; + } + + return 0; + } + + reinit_completion(&zx_i2c->complete); + + val = zx2967_i2c_readl(zx_i2c, REG_CMD); + val |= I2C_CMB_RW_EN; + zx2967_i2c_writel(zx_i2c, val, REG_CMD); + + val = zx2967_i2c_readl(zx_i2c, REG_CMD); + val |= I2C_START; + zx2967_i2c_writel(zx_i2c, val, REG_CMD); + + time_left = wait_for_completion_timeout(&zx_i2c->complete, + I2C_TIMEOUT); + if (time_left == 0) { + dev_err(zx_i2c->dev, "i2c read transfer timed out\n"); + disable_irq(zx_i2c->irq); + zx2967_i2c_reset_hardware(zx_i2c); + return -EIO; + } + + usleep_range(1000, 2000); + switch (size) { + case I2C_SMBUS_BYTE: + case I2C_SMBUS_BYTE_DATA: + val = zx2967_i2c_readl(zx_i2c, REG_DATA); + data->byte = val; + break; + case I2C_SMBUS_WORD_DATA: + case I2C_SMBUS_PROC_CALL: + buf[0] = zx2967_i2c_readl(zx_i2c, REG_DATA); + buf[1] = zx2967_i2c_readl(zx_i2c, REG_DATA); + data->word = (buf[0] << 8) | buf[1]; + break; + default: + dev_warn(&adap->dev, "Unsupported transaction %d\n", size); + return -EOPNOTSUPP; + } + + return 0; +} + +static u32 zx2967_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | + I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | + I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL | + I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK; +} + +#ifdef CONFIG_PM +static int zx2967_i2c_suspend(struct device *dev) +{ + struct zx2967_i2c_info *zx_i2c = dev_get_drvdata(dev); + + zx_i2c->is_suspended = true; + if (__clk_get_enable_count(zx_i2c->clk) == 1) + clk_disable_unprepare(zx_i2c->clk); + + return 0; +} + +static int zx2967_i2c_resume(struct device *dev) +{ + struct zx2967_i2c_info *zx_i2c = dev_get_drvdata(dev); + + zx_i2c->is_suspended = false; + clk_prepare_enable(zx_i2c->clk); + + return 0; +} +static const struct dev_pm_ops zx2967_i2c_dev_pm_ops = { + .suspend = zx2967_i2c_suspend, + .resume = zx2967_i2c_resume, +}; +#define ZX2967_I2C_DEV_PM_OPS (&zx2967_i2c_dev_pm_ops) +#else +#define ZX2967_I2C_DEV_PM_OPS NULL +#endif + +static const struct i2c_algorithm zx2967_i2c_algo = { + .master_xfer = zx2967_i2c_xfer, + .smbus_xfer = zx2967_smbus_xfer, + .functionality = zx2967_i2c_func, +}; + +static const struct of_device_id zx2967_i2c_of_match[] = { + { .compatible = "zte,zx296718-i2c", }, + {}, +}; +MODULE_DEVICE_TABLE(of, zx2967_i2c_of_match); + +static int zx2967_i2c_probe(struct platform_device *pdev) +{ + struct resource *res; + struct zx2967_i2c_info *zx_i2c = NULL; + struct clk *clk; + void __iomem *reg_base; + int ret = 0; + + zx_i2c = devm_kzalloc(&pdev->dev, sizeof(*zx_i2c), GFP_KERNEL); + if (!zx_i2c) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "missing io resource\n"); + return -EINVAL; + } + + reg_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(reg_base)) + return PTR_ERR(reg_base); + + clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "missing controller clock"); + return PTR_ERR(clk); + } + + ret = clk_prepare_enable(clk); + if (ret) { + dev_err(&pdev->dev, "failed to enable i2c_clk\n"); + return ret; + } + + of_property_read_u32(pdev->dev.of_node, + "clock-frequency", &zx_i2c->clk_freq); + zx_i2c->reg_base = reg_base; + zx_i2c->clk = clk; + zx_i2c->irq = platform_get_irq(pdev, 0); + zx_i2c->id = pdev->id; + zx_i2c->dev = &pdev->dev; + + zx_i2c->pin_scl = devm_pinctrl_get_select(&pdev->dev, "scl"); + if (IS_ERR(zx_i2c->pin_scl)) + dev_info(&pdev->dev, "scl pin is not specified in dts\n"); + + zx_i2c->pin_sda = devm_pinctrl_get_select(&pdev->dev, "sda"); + if (IS_ERR(zx_i2c->pin_sda)) + dev_info(&pdev->dev, "sda pin is not specified in dts\n"); + + spin_lock_init(&zx_i2c->lock); + init_completion(&zx_i2c->complete); + platform_set_drvdata(pdev, zx_i2c); + + ret = zx2967_i2c_reset_hardware(zx_i2c); + if (ret) { + dev_err(&pdev->dev, "failed to initialize i2c controller\n"); + goto unprepare_clk; + } + + ret = devm_request_irq(&pdev->dev, zx_i2c->irq, + zx2967_i2c_isr, 0, dev_name(&pdev->dev), zx_i2c); + if (ret) { + dev_err(&pdev->dev, "failed to request irq %i\n", zx_i2c->irq); + goto unprepare_clk; + } + + i2c_set_adapdata(&zx_i2c->adap, zx_i2c); + zx_i2c->adap.owner = THIS_MODULE; + zx_i2c->adap.class = I2C_CLASS_DEPRECATED; + strlcpy(zx_i2c->adap.name, "zx2967 i2c adapter", + sizeof(zx_i2c->adap.name)); + zx_i2c->adap.algo = &zx2967_i2c_algo; + zx_i2c->adap.dev.parent = &pdev->dev; + zx_i2c->adap.nr = pdev->id; + zx_i2c->adap.dev.of_node = pdev->dev.of_node; + + ret = i2c_add_numbered_adapter(&zx_i2c->adap); + if (ret) { + dev_err(&pdev->dev, "failed to add zx2967 i2c adapter\n"); + goto unprepare_clk; + } + + return 0; + +unprepare_clk: + clk_unprepare(zx_i2c->clk); + return ret; +} + +static int zx2967_i2c_remove(struct platform_device *pdev) +{ + struct zx2967_i2c_info *zx_i2c = platform_get_drvdata(pdev); + + i2c_del_adapter(&zx_i2c->adap); + clk_unprepare(zx_i2c->clk); + + return 0; +} + +static struct platform_driver zx2967_i2c_driver = { + .probe = zx2967_i2c_probe, + .remove = zx2967_i2c_remove, + .driver = { + .name = "zx2967_i2c", + .of_match_table = zx2967_i2c_of_match, + .pm = ZX2967_I2C_DEV_PM_OPS, + }, +}; +module_platform_driver(zx2967_i2c_driver); + +MODULE_AUTHOR("Baoyou Xie "); +MODULE_DESCRIPTION("ZTE zx2967 I2C Bus Controller driver"); +MODULE_LICENSE("GPL v2");