| Message ID | 1485345118-3082-2-git-send-email-m.szyprowski@samsung.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Exynos5433/TM2: add clocks configuration for display subsystem | expand |
On Wed, Jan 25, 2017 at 12:51:57PM +0100, Marek Szyprowski wrote: > Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and > phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed > to setup initial clock configuration for display subsystem in device tree > in order to avoid dependency on the configuration left by the bootloader. > > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> > --- > drivers/clk/samsung/clk-exynos5433.c | 6 ++++-- > include/dt-bindings/clock/exynos5433.h | 5 ++++- > 2 files changed, 8 insertions(+), 3 deletions(-) > Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Sylwester, Could you provide a tag with this? Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi, On 2017년 01월 25일 20:51, Marek Szyprowski wrote: > Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and > phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed > to setup initial clock configuration for display subsystem in device tree > in order to avoid dependency on the configuration left by the bootloader. > > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> > --- > drivers/clk/samsung/clk-exynos5433.c | 6 ++++-- > include/dt-bindings/clock/exynos5433.h | 5 ++++- > 2 files changed, 8 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c > index 0db5204c307c..1ab4fca255e1 100644 > --- a/drivers/clk/samsung/clk-exynos5433.c > +++ b/drivers/clk/samsung/clk-exynos5433.c > @@ -2559,8 +2559,10 @@ static void __init exynos5433_cmu_g2d_init(struct device_node *np) > FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), > FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), > /* PHY clocks from MIPI_DPHY0 */ > - FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000), > - FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000), > + FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy", > + NULL, 0, 188000000), > + FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy", > + NULL, 0, 100000000), > /* PHY clocks from HDMI_PHY */ > FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", > NULL, 0, 300000000), > diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h > index 4fa6bb2136e3..be39d23e6a32 100644 > --- a/include/dt-bindings/clock/exynos5433.h > +++ b/include/dt-bindings/clock/exynos5433.h > @@ -771,7 +771,10 @@ > > #define CLK_PCLK_DECON 113 > > -#define DISP_NR_CLK 114 > +#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114 > +#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115 > + > +#define DISP_NR_CLK 116 > > /* CMU_AUD */ > #define CLK_MOUT_AUD_PLL_USER 1 > Looks good to me. Acked-by: Chanwoo Choi <cw00.choi@samsugn.com> -- Best Regards, Chanwoo Choi Samsung Electronics -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Cc: linux-clk@vger.kernel.org On 01/25/2017 09:06 PM, Krzysztof Kozlowski wrote: > On Wed, Jan 25, 2017 at 12:51:57PM +0100, Marek Szyprowski wrote: >> Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and >> phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed >> to setup initial clock configuration for display subsystem in device tree >> in order to avoid dependency on the configuration left by the bootloader. >> >> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> >> --- >> drivers/clk/samsung/clk-exynos5433.c | 6 ++++-- >> include/dt-bindings/clock/exynos5433.h | 5 ++++- >> 2 files changed, 8 insertions(+), 3 deletions(-) >> > Acked-by: Krzysztof Kozlowski <krzk@kernel.org> > > Sylwester, > Could you provide a tag with this? I have the tag prepared already, but please resend the patch to linux-clk@vger.kernel.org and I will reply there. The patches were sent only to the linux-samsung-soc mailing list. -- Thanks, Sylwester -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 01/27/2017 12:05 PM, Sylwester Nawrocki wrote: > Cc: linux-clk@vger.kernel.org > > On 01/25/2017 09:06 PM, Krzysztof Kozlowski wrote: >> On Wed, Jan 25, 2017 at 12:51:57PM +0100, Marek Szyprowski wrote: >>> Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and >>> phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed >>> to setup initial clock configuration for display subsystem in device tree >>> in order to avoid dependency on the configuration left by the bootloader. >>> >>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> >>> --- >>> drivers/clk/samsung/clk-exynos5433.c | 6 ++++-- >>> include/dt-bindings/clock/exynos5433.h | 5 ++++- >>> 2 files changed, 8 insertions(+), 3 deletions(-) >>> >> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> >> >> Sylwester, >> Could you provide a tag with this? > > I have the tag prepared already, but please resend the patch to > linux-clk@vger.kernel.org and I will reply there. > The patches were sent only to the linux-samsung-soc mailing list. Krzysztof, if you need this patch series as a dependency here is the tag: The following changes since commit 0c744ea4f77d72b3dcebb7a8f2684633ec79be88: Linux 4.10-rc2 (2017-01-01 14:31:53 -0800) are available in the git repository at: git://linuxtv.org/snawrocki/samsung.git tags/clk-v4.11-samsung-dphy for you to fetch changes up to 698e0d1d22346ef03d7a13fcd9c2cc86a24bf317: clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates (2017-01-27 11:34:00 +0100) ---------------------------------------------------------------- Exporting clocks for MIPI DSI DPHY and the display PLL frequency list update for Exynos5433 SoC. ---------------------------------------------------------------- Marek Szyprowski (2): clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates drivers/clk/samsung/clk-exynos5433.c | 8 ++++++-- include/dt-bindings/clock/exynos5433.h | 5 ++++- 2 files changed, 10 insertions(+), 3 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, Jan 27, 2017 at 12:34:57PM +0100, Sylwester Nawrocki wrote: > On 01/27/2017 12:05 PM, Sylwester Nawrocki wrote: > > Cc: linux-clk@vger.kernel.org > > > > On 01/25/2017 09:06 PM, Krzysztof Kozlowski wrote: > >> On Wed, Jan 25, 2017 at 12:51:57PM +0100, Marek Szyprowski wrote: > >>> Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and > >>> phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed > >>> to setup initial clock configuration for display subsystem in device tree > >>> in order to avoid dependency on the configuration left by the bootloader. > >>> > >>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> > >>> --- > >>> drivers/clk/samsung/clk-exynos5433.c | 6 ++++-- > >>> include/dt-bindings/clock/exynos5433.h | 5 ++++- > >>> 2 files changed, 8 insertions(+), 3 deletions(-) > >>> > >> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> > >> > >> Sylwester, > >> Could you provide a tag with this? > > > > I have the tag prepared already, but please resend the patch to > > linux-clk@vger.kernel.org and I will reply there. > > The patches were sent only to the linux-samsung-soc mailing list. > > Krzysztof, if you need this patch series as a dependency here is the tag: > > The following changes since commit 0c744ea4f77d72b3dcebb7a8f2684633ec79be88: > > Linux 4.10-rc2 (2017-01-01 14:31:53 -0800) > > are available in the git repository at: > > git://linuxtv.org/snawrocki/samsung.git tags/clk-v4.11-samsung-dphy > > for you to fetch changes up to 698e0d1d22346ef03d7a13fcd9c2cc86a24bf317: > > clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates > (2017-01-27 11:34:00 +0100) > Thanks, pulled. Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c index 0db5204c307c..1ab4fca255e1 100644 --- a/drivers/clk/samsung/clk-exynos5433.c +++ b/drivers/clk/samsung/clk-exynos5433.c @@ -2559,8 +2559,10 @@ static void __init exynos5433_cmu_g2d_init(struct device_node *np) FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000), FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000), /* PHY clocks from MIPI_DPHY0 */ - FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000), - FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000), + FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy", + NULL, 0, 188000000), + FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy", + NULL, 0, 100000000), /* PHY clocks from HDMI_PHY */ FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy", NULL, 0, 300000000), diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h index 4fa6bb2136e3..be39d23e6a32 100644 --- a/include/dt-bindings/clock/exynos5433.h +++ b/include/dt-bindings/clock/exynos5433.h @@ -771,7 +771,10 @@ #define CLK_PCLK_DECON 113 -#define DISP_NR_CLK 114 +#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114 +#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115 + +#define DISP_NR_CLK 116 /* CMU_AUD */ #define CLK_MOUT_AUD_PLL_USER 1
Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed to setup initial clock configuration for display subsystem in device tree in order to avoid dependency on the configuration left by the bootloader. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> --- drivers/clk/samsung/clk-exynos5433.c | 6 ++++-- include/dt-bindings/clock/exynos5433.h | 5 ++++- 2 files changed, 8 insertions(+), 3 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html