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Wed, 25 Jan 2017 11:56:01 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi , Inki Dae Subject: [PATCH 6/8] arm64: dts: exynos: Add AUD power domain to Exynos5433 SoC Date: Wed, 25 Jan 2017 12:55:40 +0100 Message-id: <1485345342-3273-7-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1485345342-3273-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrEIsWRmVeSWpSXmKPExsWy7djPc7ohkzoiDO4etrDYOGM9q8X1L89Z LSbdn8Bicf78BnaLz71HGC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKC6b lNSczLLUIn27BK6MY2dZCq4JVly+cI65gfEubxcjJ4eEgIlE68T9rBC2mMSFe+vZuhi5OIQE ljFKLHs7Acr5zChxa+VeNpiOG9s3s8JVXb60AKxdSKCBSeLcrzgQm03AUKLrbRdYg4iAvcTt J8vYQRqYBdqYJHbdagNrEBYIlJi9vwfMZhFQlbh9ugGsgVfAXWJKz0ZGiG1yEiePTQar4RTw kOh62s8EMkhC4DWbRMulYyxdjBxAjqzEpgPMEPUuEtvbJ0P1Cku8Or6FHcKWkbg8uZsFwu5n lGhq1YawZzBKnHsLDQtricPHL4LtYhbgk5i0bTozxHheiY42IYgSD4l1n+ayQoQdJZZ/s4GE w2xGiatbj7FOYJRZwMiwilEktbQ4Nz212FCvODG3uDQvXS85P3cTIzBmT/87/n4H49PmkEOM AhyMSjy8L1LaI4RYE8uKK3MPMUpwMCuJ8C6Z2BEhxJuSWFmVWpQfX1Sak1p8iFGag0VJnHfv givhQgLpiSWp2ampBalFMFkmDk6pBkbJ6nmqhbVMz1eyCS4r5L61yHTO1vI/X/88W/5dRWlO SVpF1alKpnhOKdsp/df+v/4/Oy3tRdquO3HaFe+naBy3esZamJTyTOrE0nuxvxf0Mv407rzz ptF4avmyuZ4WSc7MRaXtt/kzFuY6//seeI3Zq83ea1Un55UfSfcjjXOjVSbPvJae8EGJpTgj 0VCLuag4EQAjG+Ys1QIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMLMWRmVeSWpSXmKPExsVy+t/xK7p+kzoiDG6d1rbYOGM9q8X1L89Z LSbdn8Bicf78BnaLz71HGC1mnN/HZLH2yF12i8Nv2lkdODw2repk8+jbsorR4/MmuQDmKDeb jNTElNQihdS85PyUzLx0W6XQEDddCyWFvMTcVFulCF3fkCAlhbLEnFIgz8gADTg4B7gHK+nb JbhlHDvLUnBNsOLyhXPMDYx3ebsYOTkkBEwkbmzfzAphi0lcuLeerYuRi0NIYAmjxIIze9kh nCYmiXcntzOBVLEJGEp0ve1iA7FFBOwlbj9ZBlbELNDBJPHvTgtQgoNDWMBf4sizYpAaFgFV idunG8DqeQXcJab0bGSE2CYncfLYZLDNnAIeEl1P+8HmCwHVTL25lmUCI+8CRoZVjCKppcW5 6bnFRnrFibnFpXnpesn5uZsYgQG87djPLTsYu94FH2IU4GBU4uGdkNQeIcSaWFZcmXuIUYKD WUmE16GlI0KINyWxsiq1KD++qDQntfgQoynQUROZpUST84HRlVcSb2hiaG5paGRsYWFuZKQk zjv1w5VwIYH0xJLU7NTUgtQimD4mDk6pBsY1G2de4I1X5Szi0mYST9MTv9Sgw2/87lmi/5rj wV1sLekperLT0/d8rbLjaz7SesPnbfgVNW/n19k54ub3hNuWbf325bGu/Od1TmcrPrjfsd/5 P/7kXd6XqVyZ/4T2cs95cC5p0vF9f5nvHBHQOG3MN0vwYHDnlodtC6b2LHppaPmAUev1lKlK LMUZiYZazEXFiQBkOGIhdgIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170125115601eucas1p29decb9c2daf4c3fcb9d796392f5d69ba X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1B?= =?utf-8?b?7IK87ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?utf-8?q?Marek_Szyprowski=1BSRPOL-Kernel_=28TP=29=1BSam?= =?utf-8?q?sung_Electronics=1BSenior_Software_Engineer?= X-Sender-Code: =?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170125115601eucas1p29decb9c2daf4c3fcb9d796392f5d69ba X-RootMTR: 20170125115601eucas1p29decb9c2daf4c3fcb9d796392f5d69ba References: <1485345342-3273-1-git-send-email-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This patch adds support for AUD power domain to Exynos5433 SoCs, which contains following devices: a clock controller, a pin controller, LPASS module, I2S controller, ADMA PL330 engine and UART #3 device. Signed-off-by: Marek Szyprowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 3487981726d9..24fc3b46cc40 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -377,6 +377,7 @@ #clock-cells = <1>; clock-names = "oscclk", "fout_aud_pll"; clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; + power-domains = <&pd_aud>; }; cmu_bus0: clock-controller@13600000 { @@ -553,6 +554,12 @@ #power-domain-cells = <0>; }; + pd_aud: aud-power-domain@105c40c0 { + compatible = "samsung,exynos5433-pd"; + reg = <0x105c40c0 0x20>; + #power-domain-cells = <0>; + }; + tmu_atlas0: tmu@10060000 { compatible = "samsung,exynos5433-tmu"; reg = <0x10060000 0x200>; @@ -665,6 +672,7 @@ compatible = "samsung,exynos5433-pinctrl"; reg = <0x114b0000 0x1000>; interrupts = ; + power-domains = <&pd_aud>; }; pinctrl_cpif: pinctrl@10fe0000 { @@ -1544,6 +1552,7 @@ clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>; clock-names = "sfr0_ctrl"; samsung,pmu-syscon = <&pmu_system_controller>; + power-domains = <&pd_aud>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -1557,6 +1566,7 @@ #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; + power-domains = <&pd_aud>; }; i2s0: i2s0@11440000 { @@ -1573,6 +1583,7 @@ clock-names = "iis", "i2s_opclk0", "i2s_opclk1"; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; + power-domains = <&pd_aud>; status = "disabled"; }; @@ -1585,6 +1596,7 @@ clock-names = "uart", "clk_uart_baud0"; pinctrl-names = "default"; pinctrl-0 = <&uart_aud_bus>; + power-domains = <&pd_aud>; status = "disabled"; }; };