From patchwork Tue Feb 7 18:37:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 93592 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp2338943qgi; Tue, 7 Feb 2017 10:57:27 -0800 (PST) X-Received: by 10.200.42.47 with SMTP id k44mr15478566qtk.56.1486493847252; Tue, 07 Feb 2017 10:57:27 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id t6si3643307qtd.8.2017.02.07.10.57.26 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 07 Feb 2017 10:57:27 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55952 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbAxA-00070w-PP for patch@linaro.org; Tue, 07 Feb 2017 13:57:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32840) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbAe6-0007co-NA for qemu-devel@nongnu.org; Tue, 07 Feb 2017 13:37:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cbAe5-0002nI-JH for qemu-devel@nongnu.org; Tue, 07 Feb 2017 13:37:42 -0500 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:48440) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cbAe5-0002gg-D2 for qemu-devel@nongnu.org; Tue, 07 Feb 2017 13:37:41 -0500 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1cbAdt-0005Td-4l for qemu-devel@nongnu.org; Tue, 07 Feb 2017 18:37:29 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 7 Feb 2017 18:37:18 +0000 Message-Id: <1486492645-27803-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1486492645-27803-1-git-send-email-peter.maydell@linaro.org> References: <1486492645-27803-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/13] target/arm: Add cfgend parameter for ARM CPU selection. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Julian Brown Add a new "cfgend" property which selects whether the CPU resets into big-endian mode or not. This setting affects whether we reset with SCTLR_B (ARMv6 and earlier) or SCTLR_EE (ARMv7 and later) set. Signed-off-by: Julian Brown Message-id: 11420d1c49636c1790e60578ee996e51f0f0b835.1484929304.git.julian@codesourcery.com [PMM: use error_report_err() rather than error_report(); move the integratorcp changes to their own patch; drop an unnecessary extra #include; rephrase commit message accordingly; move setting of reset_sctlr above registration of cpregs so it actually has an effect] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 7 +++++++ target/arm/cpu.c | 13 +++++++++++++ 2 files changed, 20 insertions(+) -- 2.7.4 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 39bff86..c0b3832 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -676,6 +676,13 @@ struct ARMCPU { int gic_vpribits; /* number of virtual priority bits */ int gic_vprebits; /* number of virtual preemption bits */ + /* Whether the cfgend input is high (i.e. this CPU should reset into + * big-endian mode). This setting isn't used directly: instead it modifies + * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the + * architecture version. + */ + bool cfgend; + ARMELChangeHook *el_change_hook; void *el_change_hook_opaque; }; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e9f10f7..a8cfd9d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -541,6 +541,9 @@ static Property arm_cpu_has_el2_property = static Property arm_cpu_has_el3_property = DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); +static Property arm_cpu_cfgend_property = + DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); + /* use property name "pmu" to match other archs and virt tools */ static Property arm_cpu_has_pmu_property = DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true); @@ -608,6 +611,8 @@ static void arm_cpu_post_init(Object *obj) } } + qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, + &error_abort); } static void arm_cpu_finalizefn(Object *obj) @@ -728,6 +733,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu->reset_sctlr |= (1 << 13); } + if (cpu->cfgend) { + if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { + cpu->reset_sctlr |= SCTLR_EE; + } else { + cpu->reset_sctlr |= SCTLR_B; + } + } + if (!cpu->has_el3) { /* If the has_el3 CPU property is disabled then we need to disable the * feature.